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Searched refs:VEX_4V (Results 1 – 19 of 19) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrSSE.td283 [(set VR256:$dst, (v8f32 immAllZerosV))]>, VEX_4V;
285 [(set VR256:$dst, (v4f64 immAllZerosV))]>, VEX_4V;
311 [(set VR128:$dst, (v4i32 immAllOnesV))]>, VEX_4V;
337 "movss\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XS, VEX_4V,
340 "movsd\t{$src2, $src1, $dst|$dst, $src1, $src2}">, XD, VEX_4V,
348 XS, VEX_4V, VEX_LIG;
352 XD, VEX_4V, VEX_LIG;
936 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1094 "\t{$src2, $src1, $dst|$dst, $src1, $src2}">, VEX_4V;
1206 VEX_4V;
[all …]
DX86InstrFormats.td113 class VEX_4V : VEX { bit hasVEX_4VPrefix = 1; }
471 OpSize, VEX_4V, Requires<[HasAVX, HasCLMUL]>;
477 OpSize, VEX_4V, Requires<[HasFMA3]>;
DX86InstrArithmetic.td1171 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8, VEX_4V;
1172 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8, VEX_4V, VEX_W;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrSSE.td200 VEX_4V, VEX_LIG, VEX_WIG;
671 VEX_4V, VEX_WIG;
797 VEX_4V, Sched<[SchedWriteFShuffle.XMM]>, VEX_WIG;
804 VEX_4V, Sched<[SchedWriteFShuffle.XMM]>, VEX_WIG,
921 WriteCvtI2SS>, XS, VEX_4V, VEX_LIG;
923 WriteCvtI2SS>, XS, VEX_4V, VEX_W, VEX_LIG;
925 WriteCvtI2SD>, XD, VEX_4V, VEX_LIG;
927 WriteCvtI2SD>, XD, VEX_4V, VEX_W, VEX_LIG;
1056 i32mem, "cvtsi2ss{l}", WriteCvtI2SS, 0>, XS, VEX_4V;
1058 i64mem, "cvtsi2ss{q}", WriteCvtI2SS, 0>, XS, VEX_4V, VEX_W;
[all …]
DX86InstrFormats.td216 class VEX_4V : VEX { bit hasVEX_4V = 1; }
883 VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoVLX]>;
887 VEX_4V, FMASC, Requires<[HasFMA, NoFMA4, NoAVX512]>;
891 VEX_4V, FMASC, Requires<[HasFMA, NoAVX512]>;
897 VEX_4V, FMASC, Requires<[HasFMA4, NoVLX]>;
901 VEX_4V, FMASC, Requires<[HasFMA4, NoAVX512]>;
905 VEX_4V, FMASC, Requires<[HasFMA4]>;
928 VEX_4V, Requires<[HasXOP]>;
DX86InstrArithmetic.td1243 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8PS, VEX_4V;
1244 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8PS, VEX_4V, VEX_W;
1267 []>, T8XD, VEX_4V, Sched<[sched, WriteIMulH]>;
1272 []>, T8XD, VEX_4V, Sched<[sched.Folded, WriteIMulH]>;
DX86InstrInfo.td2371 T8PS, VEX_4V, Sched<[WriteALU]>;
2375 T8PS, VEX_4V, Sched<[WriteALULd]>;
2584 VEX_4V, Sched<[WriteALU]>;
2588 VEX_4V, Sched<[WriteALULd, ReadAfterLd]>;
DX86InstrAVX512.td2994 sched, HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2996 sched, prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2998 sched, HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
3000 sched, HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
3057 VEX_4V, VEX_L, Sched<[sched]>;
/external/llvm/lib/Target/X86/
DX86InstrSSE.td536 VEX_4V, VEX_LIG;
1134 itin>, VEX_4V;
1358 VEX_4V, Sched<[WriteFShuffle]>;
1365 VEX_4V, Sched<[WriteFShuffle]>;
1520 XS, VEX_4V, VEX_LIG;
1522 XS, VEX_4V, VEX_W, VEX_LIG;
1524 XD, VEX_4V, VEX_LIG;
1526 XD, VEX_4V, VEX_W, VEX_LIG;
1655 SSE_CVT_Scalar, 0>, XS, VEX_4V;
1658 SSE_CVT_Scalar, 0>, XS, VEX_4V,
[all …]
DX86InstrFormats.td192 class VEX_4V : VEX { bit hasVEX_4V = 1; }
198 class EVEX_4V : VEX_4V { Encoding OpEnc = EncEVEX; }
842 VEX_4V, Requires<[HasAVX, HasPCLMUL]>;
848 VEX_4V, FMASC, Requires<[HasFMA, NoVLX]>;
854 VEX_4V, VEX_I8IMM, FMASC, Requires<[HasFMA4]>;
872 VEX_4V, VEX_I8IMM, Requires<[HasXOP]>;
DX86InstrArithmetic.td1283 defm ANDN32 : bmi_andn<"andn{l}", GR32, i32mem, loadi32>, T8PS, VEX_4V;
1284 defm ANDN64 : bmi_andn<"andn{q}", GR64, i64mem, loadi64>, T8PS, VEX_4V, VEX_W;
1306 [], IIC_MUL8>, T8XD, VEX_4V, Sched<[WriteIMul, WriteIMulH]>;
1311 [], IIC_MUL8>, T8XD, VEX_4V, Sched<[WriteIMulLd, WriteIMulH]>;
DX86InstrInfo.td2211 []>, T8PS, VEX_4V;
2215 []>, T8PS, VEX_4V;
2328 VEX_4V;
2331 [(set RC:$dst, (Int RC:$src1, (ld_frag addr:$src2)))]>, VEX_4V;
DX86InstrAVX512.td2266 HasDQI, IsCommutable>, VEX_4V, VEX_L, PD;
2268 prdW, IsCommutable>, VEX_4V, VEX_L, PS;
2270 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PD;
2272 HasBWI, IsCommutable>, VEX_4V, VEX_L, VEX_W, PS;
2364 VEX_4V, VEX_L;
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp638 bool HasVEX_4V = TSFlags & X86II::VEX_4V; in EmitVEXOpcodePrefix()
691 uint8_t VEX_4V = 0xf; in EmitVEXOpcodePrefix() local
764 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
791 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
815 VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf; in EmitVEXOpcodePrefix()
824 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
841 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
871 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
898 VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf; in EmitVEXOpcodePrefix()
907 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
[all …]
DX86BaseInfo.h542 VEX_4V = 1ULL << VEX_4VShift, enumerator
695 bool HasVEX_4V = TSFlags & X86II::VEX_4V; in getMemoryOperandNo()
/external/llvm/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp604 bool HasVEX_4V = TSFlags & X86II::VEX_4V; in EmitVEXOpcodePrefix()
659 uint8_t VEX_4V = 0xf; in EmitVEXOpcodePrefix() local
734 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
762 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
779 VEX_4V = ~getX86RegEncoding(MI, CurOp + X86::AddrNumOperands) & 0xf; in EmitVEXOpcodePrefix()
791 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
822 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
833 VEX_4V = ~getX86RegEncoding(MI, CurOp++) & 0xf; in EmitVEXOpcodePrefix()
858 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
877 VEX_4V = ~VRegEnc & 0xf; in EmitVEXOpcodePrefix()
[all …]
DX86BaseInfo.h489 VEX_4V = 1ULL << VEX_4VShift, enumerator
660 bool HasVEX_4V = TSFlags & X86II::VEX_4V; in getMemoryOperandNo()
/external/swiftshader/third_party/LLVM/lib/Target/X86/MCTargetDesc/
DX86MCCodeEmitter.cpp391 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V) in EmitVEXOpcodePrefix()
432 unsigned char VEX_4V = 0xf; in EmitVEXOpcodePrefix() local
512 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); in EmitVEXOpcodePrefix()
531 VEX_4V = getVEXRegisterEncoding(MI, 1); in EmitVEXOpcodePrefix()
565 VEX_4V = getVEXRegisterEncoding(MI, CurOp++); in EmitVEXOpcodePrefix()
584 VEX_4V = getVEXRegisterEncoding(MI, 0); in EmitVEXOpcodePrefix()
606 unsigned char LastByte = VEX_PP | (VEX_L << 2) | (VEX_4V << 3); in EmitVEXOpcodePrefix()
869 if ((TSFlags >> X86II::VEXShift) & X86II::VEX_4V) in EncodeInstruction()
DX86BaseInfo.h388 VEX_4V = 1U << 2, enumerator
480 bool HasVEX_4V = (TSFlags >> X86II::VEXShift) & X86II::VEX_4V; in getMemoryOperandNo()