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Searched refs:VGPRSpill (Results 1 – 8 of 8) sorted by relevance

/external/llvm/lib/Target/AMDGPU/
DSIDefines.h42 VGPRSpill = 1 << 23, enumerator
DSIInstrInfo.h344 return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill; in isVGPRSpill()
348 return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill; in isVGPRSpill()
DSIInstrFormats.td45 field bits<1> VGPRSpill = 0;
81 let TSFlags{23} = VGPRSpill;
DSIInstructions.td2090 let UseNamedOperandTable = 1, VGPRSpill = 1, Uses = [EXEC] in {
2106 } // End UseNamedOperandTable = 1, VGPRSpill = 1
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIInstrFormats.td58 field bit VGPRSpill = 0;
152 let TSFlags{23} = VGPRSpill;
DSIDefines.h55 VGPRSpill = 1 << 23, enumerator
DSIInstrInfo.h495 return MI.getDesc().TSFlags & SIInstrFlags::VGPRSpill; in isVGPRSpill()
499 return get(Opcode).TSFlags & SIInstrFlags::VGPRSpill; in isVGPRSpill()
DSIInstructions.td516 let UseNamedOperandTable = 1, VGPRSpill = 1,
538 } // End UseNamedOperandTable = 1, VGPRSpill = 1, SchedRW = [WriteVMEM]