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Searched refs:VSHF (Results 1 – 19 of 19) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMSA.txt32 and pck* instructions, this is matched from MipsISD::VSHF instead of
45 it lowers directly to MipsISD::VSHF instead of using common IR.
DMipsISelLowering.h228 VSHF, // Generic shuffle enumerator
DMipsSEISelLowering.cpp2153 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2160 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2239 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2957 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0); in lowerVECTOR_SHUFFLE_VSHF()
DMipsISelLowering.cpp290 case MipsISD::VSHF: return "MipsISD::VSHF"; in getTargetNodeName()
DMipsMSAInstrInfo.td40 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
/external/llvm/lib/Target/Mips/
DMSA.txt32 and pck* instructions, this is matched from MipsISD::VSHF instead of
45 it lowers directly to MipsISD::VSHF instead of using common IR.
DMipsISelLowering.h182 VSHF, // Generic shuffle enumerator
DMipsSEISelLowering.cpp2110 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2117 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2160 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), in lowerINTRINSIC_WO_CHAIN()
2866 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op1, Op0); in lowerVECTOR_SHUFFLE_VSHF()
DMipsISelLowering.cpp212 case MipsISD::VSHF: return "MipsISD::VSHF"; in getTargetNodeName()
DMipsMSAInstrInfo.td48 def MipsVSHF : SDNode<"MipsISD::VSHF", SDT_VSHF>;
/external/v8/src/mips/
Dconstants-mips.h886 VSHF = ((0U << 23) + 21), enumerator
Ddisasm-mips.cc2419 case VSHF: in DecodeTypeMsa3R()
Dsimulator-mips.cc5150 case VSHF: { in Msa3RInstrHelper_shuffle()
5236 case VSHF: in DecodeTypeMsa3R()
Dassembler-mips.cc3492 V(vshf, VSHF) \
/external/v8/src/mips64/
Dconstants-mips64.h920 VSHF = ((0U << 23) + 21), enumerator
Ddisasm-mips64.cc2733 case VSHF: in DecodeTypeMsa3R()
Dsimulator-mips64.cc5374 case VSHF: { in Msa3RInstrHelper_shuffle()
5460 case VSHF: in DecodeTypeMsa3R()
Dassembler-mips64.cc3810 V(vshf, VSHF) \
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenDAGISel.inc28365 /* 53279*/ /*SwitchOpcode*/ 124|128,2/*380*/, TARGET_VAL(MipsISD::VSHF),// ->53663