Searched refs:VecMem (Results 1 – 2 of 2) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMParallelDSP.cpp | 121 bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, MemInstList &VecMem);
290 MemInstList &VecMem, const DataLayout &DL, in AreSequentialAccesses() argument
297 VecMem.push_back(MemOp0); in AreSequentialAccesses()
298 VecMem.push_back(MemOp1); in AreSequentialAccesses()
307 MemInstList &VecMem) { in AreSequentialLoads() argument
321 return AreSequentialAccesses<LoadInst>(Ld0, Ld1, VecMem, *DL, *SE); in AreSequentialLoads()
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| /external/clang/lib/CodeGen/ |
| D | CGExpr.cpp | 3211 Address VecMem = CreateMemTemp(E->getBase()->getType()); in EmitExtVectorElementExpr() local
3212 Builder.CreateStore(Vec, VecMem); in EmitExtVectorElementExpr()
3213 Base = MakeAddrLValue(VecMem, E->getBase()->getType(), in EmitExtVectorElementExpr()
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