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Searched refs:VecRC (Results 1 – 6 of 6) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonVExtract.cpp125 const auto &VecRC = *MRI.getRegClass(VecR); in runOnMachineFunction() local
126 int FI = MFI.CreateSpillStackObject(HRI.getSpillSize(VecRC), in runOnMachineFunction()
127 HRI.getSpillAlignment(VecRC)); in runOnMachineFunction()
131 unsigned StoreOpc = VecRC.getID() == Hexagon::HvxVRRegClassID in runOnMachineFunction()
139 unsigned VecSize = HRI.getRegSizeInBits(VecRC) / 8; in runOnMachineFunction()
DHexagonVLIWPacketizer.cpp872 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF); in canPromoteToDotNew() local
873 if (DisableVecDblNVStores && VecRC == &Hexagon::HvxWRRegClass) in canPromoteToDotNew()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3314 const TargetRegisterClass *VecRC = nullptr; in emitINSERT_DF_VIDX() local
3330 VecRC = &Mips::MSA128BRegClass; in emitINSERT_DF_VIDX()
3336 VecRC = &Mips::MSA128HRegClass; in emitINSERT_DF_VIDX()
3342 VecRC = &Mips::MSA128WRegClass; in emitINSERT_DF_VIDX()
3348 VecRC = &Mips::MSA128DRegClass; in emitINSERT_DF_VIDX()
3353 unsigned Wt = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
3371 unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
3377 unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
/external/llvm/lib/Target/Mips/
DMipsSEISelLowering.cpp3223 const TargetRegisterClass *VecRC = nullptr; in emitINSERT_DF_VIDX() local
3239 VecRC = &Mips::MSA128BRegClass; in emitINSERT_DF_VIDX()
3245 VecRC = &Mips::MSA128HRegClass; in emitINSERT_DF_VIDX()
3251 VecRC = &Mips::MSA128WRegClass; in emitINSERT_DF_VIDX()
3257 VecRC = &Mips::MSA128DRegClass; in emitINSERT_DF_VIDX()
3262 unsigned Wt = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
3280 unsigned WdTmp1 = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
3286 unsigned WdTmp2 = RegInfo.createVirtualRegister(VecRC); in emitINSERT_DF_VIDX()
/external/llvm/lib/Target/Hexagon/
DHexagonVLIWPacketizer.cpp752 const TargetRegisterClass *VecRC = HII->getRegClass(MCID, 0, HRI, MF); in canPromoteToDotNew() local
753 if (DisableVecDblNVStores && VecRC == &Hexagon::VecDblRegsRegClass) in canPromoteToDotNew()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DSIISelLowering.cpp3050 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcReg); in emitIndirectSrc() local
3054 = computeIndirectRegAndOffset(TRI, VecRC, SrcReg, Offset); in emitIndirectSrc()
3112 const TargetRegisterClass *VecRC) { in getMOVRELDPseudo() argument
3113 switch (TRI.getRegSizeInBits(*VecRC)) { in getMOVRELDPseudo()
3142 const TargetRegisterClass *VecRC = MRI.getRegClass(SrcVec->getReg()); in emitIndirectDst() local
3148 std::tie(SubReg, Offset) = computeIndirectRegAndOffset(TRI, VecRC, in emitIndirectDst()
3182 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC)); in emitIndirectDst()
3200 unsigned PhiReg = MRI.createVirtualRegister(VecRC); in emitIndirectDst()
3215 const MCInstrDesc &MovRelDesc = TII->get(getMOVRELDPseudo(TRI, VecRC)); in emitIndirectDst()