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Searched refs:__raw_readl (Results 1 – 25 of 85) sorted by relevance

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/external/u-boot/arch/arm/mach-keystone/
Dpsc.c53 ptstat = __raw_readl(KS2_PSC_BASE + PSC_REG_PSTAT); in psc_wait()
73 domain_num = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_get_domain_num()
106 v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_set_state()
123 pdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_PDCTL(domain_num)); in psc_set_state()
130 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_state()
136 ptcmd = __raw_readl(KS2_PSC_BASE + PSC_REG_PTCMD); in psc_set_state()
160 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_enable_module()
178 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_disable_module()
204 mdctl = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCTL(mod_num)); in psc_set_reset_iso()
208 v = __raw_readl(KS2_PSC_BASE + PSC_REG_MDCFG(mod_num)); in psc_set_reset_iso()
[all …]
Dddr3.c28 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) in ddr3_init_ddrphy()
34 tmp = __raw_readl(base + KS2_DDRPHY_PGCR1_OFFSET); in ddr3_init_ddrphy()
44 tmp = __raw_readl(base + KS2_DDRPHY_DCR_OFFSET); in ddr3_init_ddrphy()
63 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
97 while ((__raw_readl(base + KS2_DDRPHY_PGSR0_OFFSET) & 0x1) != 0x1) in ddr3_init_ddrphy()
114 u32 value = __raw_readl(base + KS2_DDR3_MIDR_OFFSET); in ddr3_ecc_support_rmw()
133 data = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_ecc_config()
331 u32 value = __raw_readl(base + KS2_DDR3_ECC_INT_STATUS_OFFSET); in ddr3_check_ecc_int()
349 value = __raw_readl(base + KS2_DDR3_ONE_BIT_ECC_ERR_CNT_OFFSET); in ddr3_check_ecc_int()
352 value = __raw_readl(base + in ddr3_check_ecc_int()
[all …]
Dclock.c250 return __raw_readl(KS2_REV1_DEVSPEED); in read_efuse_bootrom()
252 return __raw_readl(KS2_EFUSE_BOOTROM); in read_efuse_bootrom()
289 tmp = __raw_readl(KS2_MAINPLLCTL0); in pll_freq_get()
327 tmp = __raw_readl(reg); in pll_freq_get()
/external/u-boot/drivers/video/
Dipu_common.c163 reg = __raw_readl(clk->enable_reg); in clk_ipu_enable()
169 reg = __raw_readl(&mxc_ccm->ccdr); in clk_ipu_enable()
174 reg = __raw_readl(&mxc_ccm->clpcr); in clk_ipu_enable()
185 reg = __raw_readl(clk->enable_reg); in clk_ipu_disable()
194 reg = __raw_readl(&mxc_ccm->ccdr); in clk_ipu_disable()
199 reg = __raw_readl(&mxc_ccm->clpcr); in clk_ipu_disable()
283 #define idma_is_set(reg, dma) (__raw_readl(reg(dma)) & idma_mask(dma))
290 div = __raw_readl(DI_BS_CLKGEN0(clk->id)); in ipu_pixel_clk_recalc()
372 u32 disp_gen = __raw_readl(IPU_DISP_GEN); in ipu_pixel_clk_enable()
381 u32 disp_gen = __raw_readl(IPU_DISP_GEN); in ipu_pixel_clk_disable()
[all …]
Dipu_disp.c140 u32 dmfc_gen1 = __raw_readl(DMFC_GENERAL1); in ipu_dmfc_set_wait4eot()
194 reg = __raw_readl(DI_DW_GEN(di, wave_gen)); in ipu_di_data_pin_config()
231 reg = __raw_readl(DI_STP_REP(di, wave_gen)); in ipu_di_sync_config()
242 reg = __raw_readl(DC_MAP_CONF_VAL(ptr)); in ipu_dc_map_config()
247 reg = __raw_readl(DC_MAP_CONF_PTR(map)); in ipu_dc_map_config()
255 u32 reg = __raw_readl(DC_MAP_CONF_PTR(map)); in ipu_dc_map_clear()
283 reg = __raw_readl(DC_RL_CH(chan, event)); in ipu_dc_link_event()
386 reg = __raw_readl(DP_COM_CONF()); in ipu_dp_csc_setup()
412 reg = __raw_readl(IPU_SRM_PRI2) | 0x8; in ipu_dp_csc_setup()
468 reg = __raw_readl(DP_COM_CONF()); in ipu_dp_init()
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/external/u-boot/drivers/rtc/
Dimxdi.c81 if ((__raw_readl(&data.regs->dsr) & DSR_WEF) == 0) in clear_write_error()
108 if ((__raw_readl(&data.regs->dsr) & (DSR_WCF | DSR_WEF)) != 0) { in di_write_wait()
119 if (__raw_readl(&data.regs->dsr) & DSR_WEF) { in di_write_wait()
140 if (__raw_readl(&data.regs->dsr) & DSR_NVF) { in di_init()
155 if (__raw_readl(&data.regs->dsr) & DSR_CAF) { in di_init()
162 if (__raw_readl(&data.regs->dtcmr) == 0) { in di_init()
169 if (!(__raw_readl(&data.regs->dcr) & DCR_TCE)) { in di_init()
170 rc = DI_WRITE_WAIT(__raw_readl(&data.regs->dcr) | DCR_TCE, dcr); in di_init()
193 now = __raw_readl(&data.regs->dtcmr); in rtc_get()
/external/u-boot/arch/arm/mach-imx/mx6/
Dclock.c31 reg = __raw_readl(&imx_ccm->CCGR2); in enable_ocotp_clk()
85 reg = __raw_readl(&imx_ccm->CCGR6); in enable_usboh3_clk()
166 reg = __raw_readl(&imx_ccm->CCGR2); in enable_i2c_clk()
182 reg = __raw_readl(addr); in enable_i2c_clk()
203 reg = __raw_readl(&imx_ccm->CCGR1); in enable_spi_clk()
217 div = __raw_readl(&imx_ccm->analog_pll_sys); in decode_pll()
222 div = __raw_readl(&imx_ccm->analog_pll_528); in decode_pll()
227 div = __raw_readl(&imx_ccm->analog_usb1_pll_480_ctrl); in decode_pll()
232 div = __raw_readl(&imx_ccm->analog_pll_enet); in decode_pll()
237 div = __raw_readl(&imx_ccm->analog_pll_audio); in decode_pll()
[all …]
/external/u-boot/drivers/mtd/nand/
Ddavinci_nand.c80 *(u32 *)buf = __raw_readl(nand); in nand_davinci_read_buf()
169 ecc = __raw_readl(&(davinci_emif_regs->nandfecc[ in nand_davinci_readecc()
182 val = __raw_readl(&davinci_emif_regs->nandfcr); in nand_davinci_enable_hwecc()
484 val = __raw_readl(&davinci_emif_regs->nandfcr); in nand_davinci_4bit_enable_hwecc()
492 val = __raw_readl(&davinci_emif_regs->nand4bitecc[0]); in nand_davinci_4bit_enable_hwecc()
504 ecc[i] = __raw_readl(&davinci_emif_regs->nand4bitecc[i]) & in nand_davinci_4bit_readecc()
626 val = __raw_readl(&davinci_emif_regs->nandfsr); in nand_davinci_4bit_correct_data()
642 val = __raw_readl(&davinci_emif_regs->nanderradd1); in nand_davinci_4bit_correct_data()
659 val = __raw_readl(&davinci_emif_regs->nandfsr); in nand_davinci_4bit_correct_data()
670 val = __raw_readl(&davinci_emif_regs->nandfsr); in nand_davinci_4bit_correct_data()
[all …]
/external/u-boot/drivers/net/
Dxilinx_emaclite.c157 val = __raw_readl(reg); in wait_for_bit()
196 u32 ctrl_reg = __raw_readl(&regs->mdioctrl); in phyread()
206 *data = __raw_readl(&regs->mdiord); in phyread()
224 u32 ctrl_reg = __raw_readl(&regs->mdioctrl); in phywrite()
341 while ((__raw_readl(&regs->tx_ping_tsr) & in emaclite_start()
352 while ((__raw_readl(&regs->tx_pong_tsr) & in emaclite_start()
367 if (__raw_readl(&regs->mdioctrl) & XEL_MDIOCTRL_MDIOEN_MASK) in emaclite_start()
384 tmp = ~__raw_readl(&regs->tx_ping_tsr); in xemaclite_txbufferavailable()
386 tmp |= ~__raw_readl(&regs->tx_pong_tsr); in xemaclite_txbufferavailable()
418 reg = __raw_readl(&regs->tx_ping_tsr); in emaclite_send()
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/external/u-boot/post/cpu/mpc83xx/
Decc.c62 if (__raw_readl(&ddr->err_disable) & ECC_ERROR_ENABLE) { in ecc_post_test()
110 if (!(__raw_readl(&ddr->err_detect) & ECC_ERROR_DETECT_SBE) || in ecc_post_test()
111 (__raw_readl(&ddr->data_err_inject_hi) != in ecc_post_test()
112 (__raw_readl(&ddr->capture_data_hi) ^ pattern[0])) || in ecc_post_test()
113 (__raw_readl(&ddr->data_err_inject_lo) != in ecc_post_test()
114 (__raw_readl(&ddr->capture_data_lo) ^ pattern[1]))) { in ecc_post_test()
/external/u-boot/drivers/usb/host/
Dehci-mx5.c91 v = __raw_readl(usbother_base + in mxc_set_usbcontrol()
112 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); in mxc_set_usbcontrol()
132 v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET); in mxc_set_usbcontrol()
137 v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET); in mxc_set_usbcontrol()
152 v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET); in mxc_set_usbcontrol()
165 v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET); in mxc_set_usbcontrol()
190 v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET); in mxc_set_usbcontrol()
/external/u-boot/cmd/
Dtsi148.c91 if ((__raw_readl(&dev->uregs->vstat) & 0x00000100) != 0) in tsi148_init()
112 val = __raw_readl(&dev->uregs->vstat); in tsi148_init()
204 i, ntohl(__raw_readl(&dev->uregs->outbound[i].otat))); in tsi148_pci_slave_window()
206 i, ntohl(__raw_readl(&dev->uregs->outbound[i].otsal))); in tsi148_pci_slave_window()
208 i, ntohl(__raw_readl(&dev->uregs->outbound[i].oteal))); in tsi148_pci_slave_window()
210 i, ntohl(__raw_readl(&dev->uregs->outbound[i].otofl))); in tsi148_pci_slave_window()
297 i, ntohl(__raw_readl(&dev->uregs->inbound[i].itat))); in tsi148_vme_slave_window()
299 i, ntohl(__raw_readl(&dev->uregs->inbound[i].itsal))); in tsi148_vme_slave_window()
301 i, ntohl(__raw_readl(&dev->uregs->inbound[i].iteal))); in tsi148_vme_slave_window()
303 i, ntohl(__raw_readl(&dev->uregs->inbound[i].itofl))); in tsi148_vme_slave_window()
/external/u-boot/drivers/dma/
Dti-edma3.c99 opt = __raw_readl(&rg->opt); in edma3_set_dest()
130 src_dst_bidx = __raw_readl(&rg->src_dst_bidx); in edma3_set_dest_index()
131 src_dst_cidx = __raw_readl(&rg->src_dst_cidx); in edma3_set_dest_index()
170 opt = __raw_readl(&rg->opt); in edma3_set_src()
201 src_dst_bidx = __raw_readl(&rg->src_dst_bidx); in edma3_set_src_index()
202 src_dst_cidx = __raw_readl(&rg->src_dst_cidx); in edma3_set_src_index()
261 link_bcntrld = __raw_readl(&rg->link_bcntrld); in edma3_set_transfer_params()
266 opt = __raw_readl(&rg->opt); in edma3_set_transfer_params()
314 *p++ = __raw_readl(addr++); in edma3_read_slot()
362 if (!(__raw_readl(ipr_base) & inum)) in edma3_check_for_transfer()
/external/u-boot/drivers/serial/
Dserial_linflexuart.c59 if (!(__raw_readl(&base->uartsr) & UARTSR_RMB)) in _linflex_serial_getc()
62 c = __raw_readl(&base->bdrm); in _linflex_serial_getc()
98 while ((__raw_readl(&base->linsr) & LINSR_LINS_MASK) != in _linflex_serial_init()
111 ctrl = __raw_readl(&base->lincr1); in _linflex_serial_init()
154 uint32_t uartsr = __raw_readl(&priv->lfuart->uartsr); in linflex_serial_pending()
/external/u-boot/cmd/ti/
Dddr3.c47 value = __raw_readl(index); in ddr_memory_test()
50 index, value, __raw_readl(index)); in ddr_memory_test()
73 value = __raw_readl(index); in ddr_memory_test()
76 index, value, __raw_readl(index)); in ddr_memory_test()
144 value = __raw_readl(index); in ddr_memory_compare()
145 value2 = __raw_readl(index2); in ddr_memory_compare()
/external/u-boot/arch/arm/cpu/armv8/zynqmp/
Dpsu_spl_init.c17 while ((__raw_readl(add) & mask) != value) { in mask_pollonvalue()
30 while (!(__raw_readl(addr) & mask)) { in mask_poll()
42 return __raw_readl(addr) & mask; in mask_read()
/external/u-boot/drivers/memory/
Dti-aemif.c42 tmp = __raw_readl(AEMIF_NAND_CONTROL); in aemif_configure()
47 tmp = __raw_readl(AEMIF_ONENAND_CONTROL); in aemif_configure()
52 tmp = __raw_readl(AEMIF_CONFIG(cs)); in aemif_configure()
/external/u-boot/arch/arm/mach-imx/mx7/
Dclock_slice.c425 reg = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_set_src()
443 val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_get_src()
481 reg = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_set_prediv()
511 val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_get_prediv()
540 reg = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_set_postdiv()
560 val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_get_postdiv()
596 val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_set_autopostdiv()
636 val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_get_autopostdiv()
655 *val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_get_target_val()
737 val = __raw_readl(&imx_ccm->root[clock_id].target_root); in clock_root_enabled()
/external/u-boot/drivers/usb/gadget/
Dat91_udc.c63 __raw_readl((udc)->udp_baseaddr + (reg))
138 csr = __raw_readl(creg); in read_fifo()
186 csr = __raw_readl(creg); in read_fifo()
200 u32 csr = __raw_readl(creg); in write_fifo()
222 csr = __raw_readl(creg); in write_fifo()
486 tmp = __raw_readl(ep->creg); in at91_ep_queue()
558 csr = __raw_readl(creg); in at91_ep_set_halt()
811 u32 csr = __raw_readl(creg); in handle_ep()
836 csr = __raw_readl(creg); in handle_ep()
897 csr = __raw_readl(creg); in handle_setup()
[all …]
Datmel_usba_udc.h190 __raw_readl((udc)->regs + USBA_##reg)
194 __raw_readl((ep)->ep_regs + USBA_EPT_##reg)
198 __raw_readl((ep)->dma_regs + USBA_DMA_##reg)
/external/u-boot/arch/powerpc/cpu/mpc83xx/
Dcpu_init.c218 gd->arch.reset_status = __raw_readl(&im->reset.rsr); in cpu_init_f()
222 gd->arch.arbiter_event_attributes = __raw_readl(&im->arbiter.aeatr); in cpu_init_f()
223 gd->arch.arbiter_event_address = __raw_readl(&im->arbiter.aeadr); in cpu_init_f()
235 __raw_readl(&im->im_lbc.lcrr); in cpu_init_f()
324 temp = __raw_readl(&ehci->control); in cpu_init_f()
/external/u-boot/arch/arm/mach-imx/mx5/
Dsoc.c29 int reg = __raw_readl(ROM_SI_REV); in get_cpu_rev()
37 if ((__raw_readl(GPIO1_BASE_ADDR + 0x0) & (0x1 << 22)) == 0) in get_cpu_rev()
/external/u-boot/arch/arm/mach-imx/
Dtimer.c76 i = __raw_readl(&cur_gpt->control); in timer_init()
109 return __raw_readl(&cur_gpt->counter); /* current tick value */ in timer_read_counter()
/external/u-boot/drivers/net/fsl-mc/dpio/
Dqbman_sys.h139 uint32_t reg = __raw_readl(s->addr_cinh + offset); in qbman_cinh_read()
195 shadow[loop] = __raw_readl(s->addr_cinh + offset in qbman_cena_read()
198 shadow[loop] = __raw_readl(s->addr_cena + offset in qbman_cena_read()
/external/u-boot/drivers/gpio/
Domap_gpio.c62 l = __raw_readl(reg); in _set_gpio_direction()
81 v = __raw_readl(reg); in _get_gpio_direction()
121 return (__raw_readl(reg) & (1 << gpio)) != 0; in _get_gpio_value()

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