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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/RISCV/
Dbswap-ctlz-cttz-ctpop.ll18 ; RV32I-NEXT: slli a1, a0, 8
21 ; RV32I-NEXT: slli a0, a0, 24
22 ; RV32I-NEXT: or a0, a0, a1
23 ; RV32I-NEXT: srli a0, a0, 16
34 ; RV32I-NEXT: srli a2, a0, 8
36 ; RV32I-NEXT: srli a2, a0, 24
38 ; RV32I-NEXT: slli a2, a0, 8
41 ; RV32I-NEXT: slli a0, a0, 24
42 ; RV32I-NEXT: or a0, a0, a2
43 ; RV32I-NEXT: or a0, a0, a1
[all …]
Dfp128.ll16 ; RV32I-NEXT: lui a0, %hi(y)
17 ; RV32I-NEXT: lw a1, %lo(y)(a0)
22 ; RV32I-NEXT: addi a0, a0, %lo(y)
23 ; RV32I-NEXT: lw a2, 12(a0)
25 ; RV32I-NEXT: lw a2, 8(a0)
27 ; RV32I-NEXT: lw a0, 4(a0)
28 ; RV32I-NEXT: sw a0, 12(sp)
29 ; RV32I-NEXT: addi a0, a1, %lo(x)
30 ; RV32I-NEXT: lw a1, 12(a0)
32 ; RV32I-NEXT: lw a1, 8(a0)
[all …]
Dcalling-conv.ll25 ; RV32I-FPELIM-NEXT: mv s1, a0
26 ; RV32I-FPELIM-NEXT: mv a0, a5
32 ; RV32I-FPELIM-NEXT: add a0, a1, a0
54 ; RV32I-WITHFP-NEXT: mv s1, a0
55 ; RV32I-WITHFP-NEXT: mv a0, a5
61 ; RV32I-WITHFP-NEXT: add a0, a1, a0
84 ; RV32I-FPELIM-NEXT: addi a0, zero, 1
102 ; RV32I-WITHFP-NEXT: addi a0, zero, 1
124 ; RV32I-FPELIM-NEXT: lw a3, 12(a0)
127 ; RV32I-FPELIM-NEXT: lw a4, 4(a0)
[all …]
Dlarge-stack.ll12 ; RV32I-FPELIM-NEXT: lui a0, 74565
13 ; RV32I-FPELIM-NEXT: addi a0, a0, 1664
14 ; RV32I-FPELIM-NEXT: sub sp, sp, a0
15 ; RV32I-FPELIM-NEXT: lui a0, 74565
16 ; RV32I-FPELIM-NEXT: addi a0, a0, 1664
17 ; RV32I-FPELIM-NEXT: add sp, sp, a0
22 ; RV32I-WITHFP-NEXT: lui a0, 74565
23 ; RV32I-WITHFP-NEXT: addi a0, a0, 1680
24 ; RV32I-WITHFP-NEXT: sub sp, sp, a0
25 ; RV32I-WITHFP-NEXT: lui a0, 74565
[all …]
Dfloat-select-fcmp.ll8 ; RV32IF-NEXT: mv a0, a1
19 ; RV32IF-NEXT: fmv.w.x ft0, a0
20 ; RV32IF-NEXT: feq.s a0, ft0, ft1
21 ; RV32IF-NEXT: bnez a0, .LBB1_2
25 ; RV32IF-NEXT: fmv.x.w a0, ft0
35 ; RV32IF-NEXT: fmv.w.x ft0, a0
37 ; RV32IF-NEXT: flt.s a0, ft1, ft0
38 ; RV32IF-NEXT: bnez a0, .LBB2_2
42 ; RV32IF-NEXT: fmv.x.w a0, ft0
52 ; RV32IF-NEXT: fmv.w.x ft0, a0
[all …]
Dvararg.ll27 ; RV32I-NEXT: addi a0, sp, 24
28 ; RV32I-NEXT: sw a0, 12(sp)
29 ; RV32I-NEXT: lw a0, 20(sp)
42 ; RV32I-FPELIM-NEXT: addi a0, sp, 24
43 ; RV32I-FPELIM-NEXT: sw a0, 12(sp)
44 ; RV32I-FPELIM-NEXT: lw a0, 20(sp)
61 ; RV32I-WITHFP-NEXT: addi a0, s0, 8
62 ; RV32I-WITHFP-NEXT: sw a0, -12(s0)
63 ; RV32I-WITHFP-NEXT: lw a0, 4(s0)
91 ; RV32I-NEXT: addi a0, sp, 24
[all …]
Dfloat-fcmp.ll8 ; RV32IF-NEXT: mv a0, zero
19 ; RV32IF-NEXT: fmv.w.x ft1, a0
20 ; RV32IF-NEXT: feq.s a0, ft1, ft0
30 ; RV32IF-NEXT: fmv.w.x ft0, a0
32 ; RV32IF-NEXT: flt.s a0, ft1, ft0
42 ; RV32IF-NEXT: fmv.w.x ft0, a0
44 ; RV32IF-NEXT: fle.s a0, ft1, ft0
55 ; RV32IF-NEXT: fmv.w.x ft1, a0
56 ; RV32IF-NEXT: flt.s a0, ft1, ft0
67 ; RV32IF-NEXT: fmv.w.x ft1, a0
[all …]
Di32-icmp.ll11 ; RV32I-NEXT: xor a0, a0, a1
12 ; RV32I-NEXT: seqz a0, a0
22 ; RV32I-NEXT: xor a0, a0, a1
23 ; RV32I-NEXT: snez a0, a0
33 ; RV32I-NEXT: sltu a0, a1, a0
43 ; RV32I-NEXT: sltu a0, a0, a1
44 ; RV32I-NEXT: xori a0, a0, 1
54 ; RV32I-NEXT: sltu a0, a0, a1
64 ; RV32I-NEXT: sltu a0, a1, a0
65 ; RV32I-NEXT: xori a0, a0, 1
[all …]
Dsext-zext-trunc.ll8 ; RV32I-NEXT: andi a0, a0, 1
9 ; RV32I-NEXT: neg a0, a0
18 ; RV32I-NEXT: andi a0, a0, 1
19 ; RV32I-NEXT: neg a0, a0
28 ; RV32I-NEXT: andi a0, a0, 1
29 ; RV32I-NEXT: neg a0, a0
38 ; RV32I-NEXT: andi a0, a0, 1
39 ; RV32I-NEXT: neg a0, a0
40 ; RV32I-NEXT: mv a1, a0
49 ; RV32I-NEXT: slli a0, a0, 24
[all …]
Dhoist-global-addr-base.ll13 ; CHECK-NEXT: lui a0, %hi(s)
14 ; CHECK-NEXT: addi a0, a0, %lo(s)
16 ; CHECK-NEXT: sw a1, 164(a0)
18 ; CHECK-NEXT: sw a1, 160(a0)
29 ; CHECK-NEXT: lui a0, %hi(s)
30 ; CHECK-NEXT: addi a0, a0, %lo(s)
31 ; CHECK-NEXT: lw a1, 164(a0)
36 ; CHECK-NEXT: sw a1, 160(a0)
56 ; addi a1, a0, %lo(g)
57 ; lui a0, 18 ---> offset
[all …]
Dalu32.ll14 ; RV32I-NEXT: addi a0, a0, 1
23 ; RV32I-NEXT: slti a0, a0, 2
33 ; RV32I-NEXT: sltiu a0, a0, 3
43 ; RV32I-NEXT: xori a0, a0, 4
52 ; RV32I-NEXT: ori a0, a0, 5
61 ; RV32I-NEXT: andi a0, a0, 6
70 ; RV32I-NEXT: slli a0, a0, 7
79 ; RV32I-NEXT: srli a0, a0, 8
88 ; RV32I-NEXT: srai a0, a0, 9
99 ; RV32I-NEXT: add a0, a0, a1
[all …]
/external/clang/test/CodeGen/
Dbitfield-2.c24 int f0_load(struct s0 *a0) { in f0_load() argument
26 return a0->f0; in f0_load()
28 int f0_store(struct s0 *a0) { in f0_store() argument
29 return (a0->f0 = 1); in f0_store()
31 int f0_reload(struct s0 *a0) { in f0_reload() argument
32 return (a0->f0 += 1); in f0_reload()
70 int f1_load(struct s1 *a0) { in f1_load() argument
72 return a0->f1; in f1_load()
74 int f1_store(struct s1 *a0) { in f1_store() argument
75 return (a0->f1 = 1234); in f1_store()
[all …]
/external/v8/src/regexp/mips64/
Dregexp-macro-assembler-mips64.cc187 __ Ld(a0, register_location(reg)); in AdvanceRegister()
188 __ Daddu(a0, a0, Operand(by)); in AdvanceRegister()
189 __ Sd(a0, register_location(reg)); in AdvanceRegister()
197 Pop(a0); in Backtrack()
198 __ Daddu(a0, a0, code_pointer()); in Backtrack()
199 __ Jump(a0); in Backtrack()
220 __ Daddu(a0, current_input_offset(), Operand(-char_size())); in CheckAtStart()
221 BranchOrBacktrack(on_at_start, eq, a0, Operand(a1)); in CheckAtStart()
228 __ Daddu(a0, current_input_offset(), in CheckNotAtStart()
230 BranchOrBacktrack(on_not_at_start, ne, a0, Operand(a1)); in CheckNotAtStart()
[all …]
/external/v8/src/regexp/mips/
Dregexp-macro-assembler-mips.cc150 __ lw(a0, register_location(reg)); in AdvanceRegister()
151 __ Addu(a0, a0, Operand(by)); in AdvanceRegister()
152 __ sw(a0, register_location(reg)); in AdvanceRegister()
160 Pop(a0); in Backtrack()
161 __ Addu(a0, a0, code_pointer()); in Backtrack()
162 __ Jump(a0); in Backtrack()
183 __ Addu(a0, current_input_offset(), Operand(-char_size())); in CheckAtStart()
184 BranchOrBacktrack(on_at_start, eq, a0, Operand(a1)); in CheckAtStart()
191 __ Addu(a0, current_input_offset(), in CheckNotAtStart()
193 BranchOrBacktrack(on_not_at_start, ne, a0, Operand(a1)); in CheckNotAtStart()
[all …]
/external/python/cpython2/Include/
DPython-ast.h375 #define Module(a0, a1) _Py_Module(a0, a1) argument
377 #define Interactive(a0, a1) _Py_Interactive(a0, a1) argument
379 #define Expression(a0, a1) _Py_Expression(a0, a1) argument
381 #define Suite(a0, a1) _Py_Suite(a0, a1) argument
383 #define FunctionDef(a0, a1, a2, a3, a4, a5, a6) _Py_FunctionDef(a0, a1, a2, a3, a4, a5, a6) argument
387 #define ClassDef(a0, a1, a2, a3, a4, a5, a6) _Py_ClassDef(a0, a1, a2, a3, a4, a5, a6) argument
391 #define Return(a0, a1, a2, a3) _Py_Return(a0, a1, a2, a3) argument
393 #define Delete(a0, a1, a2, a3) _Py_Delete(a0, a1, a2, a3) argument
396 #define Assign(a0, a1, a2, a3, a4) _Py_Assign(a0, a1, a2, a3, a4) argument
399 #define AugAssign(a0, a1, a2, a3, a4, a5) _Py_AugAssign(a0, a1, a2, a3, a4, a5) argument
[all …]
/external/python/cpython3/Include/
DPython-ast.h442 #define Module(a0, a1) _Py_Module(a0, a1) argument
444 #define Interactive(a0, a1) _Py_Interactive(a0, a1) argument
446 #define Expression(a0, a1) _Py_Expression(a0, a1) argument
448 #define Suite(a0, a1) _Py_Suite(a0, a1) argument
450 #define FunctionDef(a0, a1, a2, a3, a4, a5, a6, a7) _Py_FunctionDef(a0, a1, a2, a3, a4, a5, a6, a7) argument
454 #define AsyncFunctionDef(a0, a1, a2, a3, a4, a5, a6, a7) _Py_AsyncFunctionDef(a0, a1, a2, a3, a4, a… argument
458 #define ClassDef(a0, a1, a2, a3, a4, a5, a6, a7) _Py_ClassDef(a0, a1, a2, a3, a4, a5, a6, a7) argument
462 #define Return(a0, a1, a2, a3) _Py_Return(a0, a1, a2, a3) argument
464 #define Delete(a0, a1, a2, a3) _Py_Delete(a0, a1, a2, a3) argument
467 #define Assign(a0, a1, a2, a3, a4) _Py_Assign(a0, a1, a2, a3, a4) argument
[all …]
/external/syzkaller/sys/test/
Dtest.txt10 test$int(a0 intptr, a1 int8, a2 int16, a3 int32, a4 int64)
14 test$opt0(a0 intptr[opt])
15 test$opt1(a0 ptr[in, intptr, opt])
16 test$opt2(a0 vma[opt])
17 test$opt3(a0 proc[100, 4, opt])
21 test$align0(a0 ptr[in, syz_align0])
22 test$align1(a0 ptr[in, syz_align1])
23 test$align2(a0 ptr[in, syz_align2])
24 test$align3(a0 ptr[in, syz_align3])
25 test$align4(a0 ptr[in, syz_align4])
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/RISCV/
Drv64-relaxation.s20 c.bnez a0, NEAR
21 #INSTR: c.bnez a0, 56
22 #RELAX-INSTR: c.bnez a0, 0
24 c.bnez a0, NEAR_NEGATIVE
25 #INSTR: c.bnez a0, -4
26 #RELAX-INSTR: c.bnez a0, 0
28 c.bnez a0, FAR_BRANCH
29 #INSTR-NEXT: bne a0, zero, 310
30 #RELAX-INSTR-NEXT: bne a0, zero, 0
32 c.bnez a0, FAR_BRANCH_NEGATIVE
[all …]
Drv32-relaxation.s20 c.bnez a0, NEAR
21 #INSTR: c.bnez a0, 72
22 #RELAX-INSTR: c.bnez a0, 0
24 c.bnez a0, NEAR_NEGATIVE
25 #INSTR: c.bnez a0, -4
26 #RELAX-INSTR: c.bnez a0, 0
28 c.bnez a0, FAR_BRANCH
29 #INSTR-NEXT: bne a0, zero, 326
30 #RELAX-INSTR-NEXT: bne a0, zero, 0
32 c.bnez a0, FAR_BRANCH_NEGATIVE
[all …]
/external/pdfium/third_party/libtiff/
Dtif_fax3.h224 printf("SETVALUE: %d\t%d\n", RunLength + (x), a0); \
225 a0 += x; \
246 a0 += (x); \
290 if (a0 != lastx) { \
291 badlength(a0, lastx); \
292 while (a0 > lastx && pa > thisrun) \
293 a0 -= *--pa; \
294 if (a0 < lastx) { \
295 if (a0 < 0) \
296 a0 = 0; \
[all …]
/external/swiftshader/third_party/LLVM/test/CodeGen/Mips/
Dmips64shift.ll3 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
6 %shl = shl i64 %a0, %a1
10 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
13 %shr = ashr i64 %a0, %a1
17 define i64 @f2(i64 %a0, i64 %a1) nounwind readnone {
20 %shr = lshr i64 %a0, %a1
24 define i64 @f3(i64 %a0) nounwind readnone {
27 %shl = shl i64 %a0, 10
31 define i64 @f4(i64 %a0) nounwind readnone {
34 %shr = ashr i64 %a0, 10
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Mips/
Dmips64shift.ll3 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
6 %shl = shl i64 %a0, %a1
10 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
13 %shr = ashr i64 %a0, %a1
17 define i64 @f2(i64 %a0, i64 %a1) nounwind readnone {
20 %shr = lshr i64 %a0, %a1
24 define i64 @f3(i64 %a0) nounwind readnone {
27 %shl = shl i64 %a0, 10
31 define i64 @f4(i64 %a0) nounwind readnone {
34 %shr = ashr i64 %a0, 10
[all …]
/external/llvm/test/CodeGen/Mips/
Dmips64shift.ll4 define i64 @f0(i64 %a0, i64 %a1) nounwind readnone {
7 %shl = shl i64 %a0, %a1
11 define i64 @f1(i64 %a0, i64 %a1) nounwind readnone {
14 %shr = ashr i64 %a0, %a1
18 define i64 @f2(i64 %a0, i64 %a1) nounwind readnone {
21 %shr = lshr i64 %a0, %a1
25 define i64 @f3(i64 %a0) nounwind readnone {
28 %shl = shl i64 %a0, 10
32 define i64 @f4(i64 %a0) nounwind readnone {
35 %shr = ashr i64 %a0, 10
[all …]
/external/v8/src/mips64/
Dcodegen-mips64.cc68 __ mov(v0, a0); // In delay slot. in CreateMemCopyUint8Function()
74 __ xor_(t8, a1, a0); in CreateMemCopyUint8Function()
77 __ subu(a3, zero_reg, a0); // In delay slot. in CreateMemCopyUint8Function()
86 __ swr(t8, MemOperand(a0)); in CreateMemCopyUint8Function()
87 __ addu(a0, a0, a3); in CreateMemCopyUint8Function()
91 __ swl(t8, MemOperand(a0)); in CreateMemCopyUint8Function()
92 __ addu(a0, a0, a3); in CreateMemCopyUint8Function()
103 __ addu(a3, a0, a3); // Now a3 is the final dst after loop. in CreateMemCopyUint8Function()
111 __ addu(a4, a0, a2); // a4 is the "past the end" address. in CreateMemCopyUint8Function()
121 __ Pref(pref_hint_store, MemOperand(a0, 1 * pref_chunk)); in CreateMemCopyUint8Function()
[all …]
/external/v8/src/mips/
Dcodegen-mips.cc69 __ mov(v0, a0); // In delay slot. in CreateMemCopyUint8Function()
75 __ xor_(t8, a1, a0); in CreateMemCopyUint8Function()
78 __ subu(a3, zero_reg, a0); // In delay slot. in CreateMemCopyUint8Function()
87 __ swr(t8, MemOperand(a0)); in CreateMemCopyUint8Function()
88 __ addu(a0, a0, a3); in CreateMemCopyUint8Function()
92 __ swl(t8, MemOperand(a0)); in CreateMemCopyUint8Function()
93 __ addu(a0, a0, a3); in CreateMemCopyUint8Function()
103 __ addu(a3, a0, a3); // Now a3 is the final dst after loop. in CreateMemCopyUint8Function()
111 __ addu(t0, a0, a2); // t0 is the "past the end" address. in CreateMemCopyUint8Function()
121 __ Pref(pref_hint_store, MemOperand(a0, 1 * pref_chunk)); in CreateMemCopyUint8Function()
[all …]

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