1; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
3; RUN:   | FileCheck -check-prefix=RV32I %s
4
5@x = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
6@y = local_unnamed_addr global fp128 0xL00000000000000007FFF000000000000, align 16
7
8; Besides anything else, these tests help verify that libcall ABI lowering
9; works correctly
10
11define i32 @test_load_and_cmp() nounwind {
12; RV32I-LABEL: test_load_and_cmp:
13; RV32I:       # %bb.0:
14; RV32I-NEXT:    addi sp, sp, -48
15; RV32I-NEXT:    sw ra, 44(sp)
16; RV32I-NEXT:    lui a0, %hi(y)
17; RV32I-NEXT:    lw a1, %lo(y)(a0)
18; RV32I-NEXT:    sw a1, 8(sp)
19; RV32I-NEXT:    lui a1, %hi(x)
20; RV32I-NEXT:    lw a2, %lo(x)(a1)
21; RV32I-NEXT:    sw a2, 24(sp)
22; RV32I-NEXT:    addi a0, a0, %lo(y)
23; RV32I-NEXT:    lw a2, 12(a0)
24; RV32I-NEXT:    sw a2, 20(sp)
25; RV32I-NEXT:    lw a2, 8(a0)
26; RV32I-NEXT:    sw a2, 16(sp)
27; RV32I-NEXT:    lw a0, 4(a0)
28; RV32I-NEXT:    sw a0, 12(sp)
29; RV32I-NEXT:    addi a0, a1, %lo(x)
30; RV32I-NEXT:    lw a1, 12(a0)
31; RV32I-NEXT:    sw a1, 36(sp)
32; RV32I-NEXT:    lw a1, 8(a0)
33; RV32I-NEXT:    sw a1, 32(sp)
34; RV32I-NEXT:    lw a0, 4(a0)
35; RV32I-NEXT:    sw a0, 28(sp)
36; RV32I-NEXT:    addi a0, sp, 24
37; RV32I-NEXT:    addi a1, sp, 8
38; RV32I-NEXT:    call __netf2
39; RV32I-NEXT:    xor a0, a0, zero
40; RV32I-NEXT:    snez a0, a0
41; RV32I-NEXT:    lw ra, 44(sp)
42; RV32I-NEXT:    addi sp, sp, 48
43; RV32I-NEXT:    ret
44  %1 = load fp128, fp128* @x, align 16
45  %2 = load fp128, fp128* @y, align 16
46  %cmp = fcmp une fp128 %1, %2
47  %3 = zext i1 %cmp to i32
48  ret i32 %3
49}
50
51define i32 @test_add_and_fptosi() nounwind {
52; RV32I-LABEL: test_add_and_fptosi:
53; RV32I:       # %bb.0:
54; RV32I-NEXT:    addi sp, sp, -80
55; RV32I-NEXT:    sw ra, 76(sp)
56; RV32I-NEXT:    lui a0, %hi(y)
57; RV32I-NEXT:    lw a1, %lo(y)(a0)
58; RV32I-NEXT:    sw a1, 24(sp)
59; RV32I-NEXT:    lui a1, %hi(x)
60; RV32I-NEXT:    lw a2, %lo(x)(a1)
61; RV32I-NEXT:    sw a2, 40(sp)
62; RV32I-NEXT:    addi a0, a0, %lo(y)
63; RV32I-NEXT:    lw a2, 12(a0)
64; RV32I-NEXT:    sw a2, 36(sp)
65; RV32I-NEXT:    lw a2, 8(a0)
66; RV32I-NEXT:    sw a2, 32(sp)
67; RV32I-NEXT:    lw a0, 4(a0)
68; RV32I-NEXT:    sw a0, 28(sp)
69; RV32I-NEXT:    addi a0, a1, %lo(x)
70; RV32I-NEXT:    lw a1, 12(a0)
71; RV32I-NEXT:    sw a1, 52(sp)
72; RV32I-NEXT:    lw a1, 8(a0)
73; RV32I-NEXT:    sw a1, 48(sp)
74; RV32I-NEXT:    lw a0, 4(a0)
75; RV32I-NEXT:    sw a0, 44(sp)
76; RV32I-NEXT:    addi a0, sp, 56
77; RV32I-NEXT:    addi a1, sp, 40
78; RV32I-NEXT:    addi a2, sp, 24
79; RV32I-NEXT:    call __addtf3
80; RV32I-NEXT:    lw a0, 68(sp)
81; RV32I-NEXT:    sw a0, 20(sp)
82; RV32I-NEXT:    lw a0, 64(sp)
83; RV32I-NEXT:    sw a0, 16(sp)
84; RV32I-NEXT:    lw a0, 60(sp)
85; RV32I-NEXT:    sw a0, 12(sp)
86; RV32I-NEXT:    lw a0, 56(sp)
87; RV32I-NEXT:    sw a0, 8(sp)
88; RV32I-NEXT:    addi a0, sp, 8
89; RV32I-NEXT:    call __fixtfsi
90; RV32I-NEXT:    lw ra, 76(sp)
91; RV32I-NEXT:    addi sp, sp, 80
92; RV32I-NEXT:    ret
93  %1 = load fp128, fp128* @x, align 16
94  %2 = load fp128, fp128* @y, align 16
95  %3 = fadd fp128 %1, %2
96  %4 = fptosi fp128 %3 to i32
97  ret i32 %4
98}
99