| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/ |
| D | MachineIRBuilder.cpp | 156 .addDef(Res) in buildFrameIndex()
168 .addDef(Res) in buildGlobalValue()
188 .addDef(Res) in buildGEP()
218 .addDef(Res) in buildPtrMask()
235 return buildInstr(TargetOpcode::COPY).addDef(Res).addUse(Op); in buildCopy()
249 return buildInstr(TargetOpcode::G_CONSTANT).addDef(Res).addCImm(NewVal); in buildConstant()
264 return buildInstr(TargetOpcode::G_FCONSTANT).addDef(Res).addFPImm(&Val); in buildFConstant()
295 .addDef(Res) in buildLoadInstr()
324 .addDef(Res) in buildUAdde()
325 .addDef(CarryOut) in buildUAdde()
[all …]
|
| D | IRTranslator.cpp | 282 MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op0).addUse(Op1); in translateBinaryOp()
291 .addDef(getOrCreateVReg(U)) in translateFSub()
577 MIRBuilder.buildInstr(Opcode).addDef(Res).addUse(Op); in translateCast()
699 MIB.addDef(DstReg); in getStackGuard()
720 .addDef(ResRegs[0]) in translateOverflowIntrinsic()
721 .addDef(ResRegs[1]) in translateOverflowIntrinsic()
823 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
829 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
834 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
839 .addDef(getOrCreateVReg(CI)) in translateKnownIntrinsic()
[all …]
|
| D | LegalizerHelper.cpp | 829 .addDef(QuotReg) in lower()
857 .addDef(HiPart) in lower()
871 .addDef(Shifted) in lower()
909 .addDef(Res) in lower()
925 MIRBuilder.buildInstr(TargetOpcode::G_FNEG).addDef(Neg).addUse(RHS); in lower()
927 .addDef(Res) in lower()
|
| D | RegBankSelect.cpp | 163 MIRBuilder.buildInstrNoInsert(TargetOpcode::COPY).addDef(Dst).addUse(Src); in repairReg()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | ShadowCallStack.cpp | 96 addDirectMem(BuildMI(MBB, MBBI, DL, TII->get(X86::MOV64rm)).addDef(ReturnReg), in addProlog()
100 .addDef(OffsetReg) in addProlog()
109 BuildMI(MBB, MBBI, DL, TII->get(X86::MOV64rm)).addDef(OffsetReg), X86::GS, in addProlog()
122 .addDef(FreeRegister), in addPrologLeaf()
132 .addDef(X86::R11) in addEpilog()
136 addSegmentedMem(BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm)).addDef(X86::R10), in addEpilog()
139 addSegmentedMem(BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm)).addDef(X86::R10), in addEpilog()
173 .addDef(X86::R10) in addEpilogOnlyR10()
177 addSegmentedMem(BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm)).addDef(X86::R10), in addEpilogOnlyR10()
180 addSegmentedMem(BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm)).addDef(X86::R10), in addEpilogOnlyR10()
|
| D | X86CallLowering.cpp | 307 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
427 .addDef(X86::AL) in lowerCall()
|
| D | X86InstructionSelector.cpp | 256 .addDef(ExtSrc) in selectCopy()
812 .addDef(TransitRegTo) in selectZext()
818 .addDef(DstReg) in selectZext()
909 .addDef(DstReg) in selectAnyext()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
| D | MipsInstructionSelector.cpp | 153 .addDef(LUiReg) in select()
157 .addDef(I.getOperand(0).getReg()) in select()
178 .addDef(LUiReg) in select()
183 .addDef(I.getOperand(0).getReg()) in select()
|
| D | MipsCallLowering.cpp | 80 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
328 MIB.addDef(Mips::SP, RegState::Implicit); in lowerCall()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/GlobalISel/ |
| D | ConstantFoldingMIRBuilder.h | 88 return buildInstr(Opcode).addDef(Dst).addUse(Src0).addUse(Src1); in buildBinaryOp()
122 return buildInstr(Opc).addDef(Dst).addUse(Src0).addUse(Src1); in buildInstr()
129 auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty)); in buildInstr()
|
| D | MachineIRBuilder.h | 1074 return buildInstr(Opcode).addDef(Dst).addUse(Src0).addUse(Src1); in buildBinaryOp()
1086 auto MIB = buildInstr(Opc).addDef(getDestFromArg(Ty)); in buildInstr()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstructionSelector.cpp | 330 .addDef(CopyReg) in selectFP16CopyFromGPR32()
334 .addDef(SubRegCopy) in selectFP16CopyFromGPR32()
404 .addDef(PromoteReg) in selectCopy()
645 .addDef(ArgsAddrReg) in selectVaStartDarwin()
682 auto MovI = MIB.buildInstr(AArch64::MOVKXi).addDef(DstReg).addUse(SrcReg); in materializeLargeCMVal()
866 .addDef(DefReg) in select()
912 .addDef(I.getOperand(0).getReg()) in select()
945 .addDef(SrcReg) in select()
1244 .addDef(ExtSrc) in select()
1281 .addDef(SrcXReg) in select()
[all …]
|
| D | AArch64CallLowering.cpp | 119 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstructionSelector.cpp | 385 .addDef(DestReg) in putConstant()
488 .addDef(ResReg) in insertComparison()
645 .addDef(ResReg) in selectSelect()
718 .addDef(SExtResult) in select()
767 .addDef(DstReg) in select()
768 .addDef(IgnoredBits) in select()
|
| D | Thumb1FrameLowering.cpp | 368 .addDef(ARM::CPSR) in emitPrologue()
374 .addDef(ARM::CPSR) in emitPrologue()
|
| D | ARMCallLowering.cpp | 488 MIB.addDef(PhysReg, RegState::Implicit); in markPhysRegUsed()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/ |
| D | LiveDebugVariables.cpp | 263 void addDef(SlotIndex Idx, const MachineOperand &LocMO, bool IsIndirect) { in addDef() function in __anon4052aede0211::UserValue
565 UV->addDef(Idx, MI.getOperand(0), IsIndirect); in handleDebugValue()
569 UV->addDef(Idx, MO, false); in handleDebugValue()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/ |
| D | SIFormMemoryClauses.cpp | 368 B.addDef(R.first, S, SubReg); in runOnMachineFunction()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonFrameLowering.cpp | 642 .addDef(Hexagon::D15) in insertEpilogueInBlock()
690 .addDef(Hexagon::D15) in insertEpilogueInBlock()
696 .addDef(Hexagon::D15) in insertEpilogueInBlock()
725 .addDef(SP) in insertAllocframe()
737 .addDef(SP) in insertAllocframe()
|
| /external/swiftshader/third_party/LLVM/lib/CodeGen/ |
| D | LiveDebugVariables.cpp | 204 void addDef(SlotIndex Idx, const MachineOperand &LocMO) { in addDef() function in __anon008224d20211::UserValue
453 UV->addDef(Idx, MI->getOperand(0)); in handleDebugValue()
|
| /external/llvm/lib/TableGen/ |
| D | TGParser.cpp | 350 Records.addDef(std::move(IterRec)); in ProcessForeachDefs()
1219 Records.addDef(std::move(NewRecOwner)); in ParseSimpleValue()
2001 Records.addDef(std::move(CurRecOwner)); in ParseDef()
2424 Records.addDef(std::move(CurRec)); in InstantiateMulticlassDef()
|
| /external/llvm/lib/CodeGen/ |
| D | LiveDebugVariables.cpp | 214 void addDef(SlotIndex Idx, const MachineOperand &LocMO) { in addDef() function in __anonb2ee42a60211::UserValue
507 UV->addDef(Idx, MI.getOperand(0)); in handleDebugValue()
|
| /external/deqp-deps/glslang/StandAlone/ |
| D | StandAlone.cpp | 197 void addDef(std::string def) in addDef() function in TPreamble
625 UserPreamble.addDef(getStringOperand("-D<macro> macro name")); in ProcessArguments()
|
| /external/swiftshader/third_party/LLVM/lib/TableGen/ |
| D | TGParser.cpp | 1113 Records.addDef(NewRec); in ParseSimpleValue()
1684 Records.addDef(CurRec); in ParseDef()
2027 Records.addDef(CurRec); in ResolveMulticlassDef()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/ |
| D | MachineInstrBuilder.h | 103 const MachineInstrBuilder &addDef(unsigned RegNo, unsigned Flags = 0,
|