| /external/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 617 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
620 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
637 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
639 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
643 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
645 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
649 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
687 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
690 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeDaddiGroupBranch()
707 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP37GroupBranchMMR6()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/Disassembler/ |
| D | MipsDisassembler.cpp | 636 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
638 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATIMMR6()
650 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
652 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR64RegClassID, in DecodeDAHIDATI()
688 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
691 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodeAddiGroupBranch()
708 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
710 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
715 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
717 MI.addOperand(MCOperand::createReg(getReg(Decoder, Mips::GPR32RegClassID, in DecodePOP35GroupBranchMMR6()
[all …]
|
| /external/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 257 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
325 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateSrcIndex()
329 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateSrcIndex()
350 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateDstIndex()
616 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
619 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
622 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); in translateImmediate()
625 mcInst.addOperand(MCOperand::createReg(X86::BND0 + (immediate >> 4))); in translateImmediate()
658 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateImmediate()
691 mcInst.addOperand(MCOperand::createReg(X86::x)); break; in translateRMRegister()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/Disassembler/ |
| D | X86Disassembler.cpp | 274 mcInst.addOperand(MCOperand::createReg(llvmRegnum)); in translateRegister()
342 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateSrcIndex()
346 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateSrcIndex()
367 MCOperand baseReg = MCOperand::createReg(baseRegNo); in translateDstIndex()
658 mcInst.addOperand(MCOperand::createReg(X86::XMM0 + (immediate >> 4))); in translateImmediate()
661 mcInst.addOperand(MCOperand::createReg(X86::YMM0 + (immediate >> 4))); in translateImmediate()
664 mcInst.addOperand(MCOperand::createReg(X86::ZMM0 + (immediate >> 4))); in translateImmediate()
678 segmentReg = MCOperand::createReg(segmentRegnums[insn.segmentOverride]); in translateImmediate()
711 mcInst.addOperand(MCOperand::createReg(X86::x)); break; in translateRMRegister()
756 baseReg = MCOperand::createReg(X86::x); break; in translateRMMemory()
[all …]
|
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| D | HexagonDisassembler.cpp | 476 Inst.addOperand(MCOperand::createReg(Table[RegNo])); in DecodeRegisterClass()
578 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCtrRegsRegisterClass()
602 Inst.addOperand(MCOperand::createReg(Register)); in DecodeCtrRegs64RegisterClass()
620 Inst.addOperand(MCOperand::createReg(Register)); in DecodeModRegsRegisterClass()
1386 Op = MCOperand::createReg(operand); in addSubinstOperands()
1389 Op = MCOperand::createReg(operand); in addSubinstOperands()
1397 Op = MCOperand::createReg(operand); in addSubinstOperands()
1400 Op = MCOperand::createReg(operand); in addSubinstOperands()
1408 Op = MCOperand::createReg(operand); in addSubinstOperands()
1411 Op = MCOperand::createReg(operand); in addSubinstOperands()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 518 MOVI.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
527 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
528 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
532 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
533 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
537 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
538 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); in EmitFMov0()
573 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
596 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
628 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 89 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
297 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
307 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
318 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
320 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
330 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr20Operand()
332 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr20Operand()
342 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len4Operand()
354 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len8Operand()
366 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDRAddr12Operand()
[all …]
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64AsmPrinter.cpp | 435 MOVI.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
444 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
445 FMov.addOperand(MCOperand::createReg(AArch64::WZR)); in EmitFMov0()
449 FMov.addOperand(MCOperand::createReg(DestReg)); in EmitFMov0()
450 FMov.addOperand(MCOperand::createReg(AArch64::XZR)); in EmitFMov0()
494 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg())); in EmitInstruction()
527 Adrp.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
533 Ldr.addOperand(MCOperand::createReg(AArch64::X1)); in EmitInstruction()
534 Ldr.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
541 Add.addOperand(MCOperand::createReg(AArch64::X0)); in EmitInstruction()
[all …]
|
| /external/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.cpp | 41 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoopForMachoTarget()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
48 NopInst.addOperand(MCOperand::createReg(0)); in getNoopForMachoTarget()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMInstrInfo.cpp | 41 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
44 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoop()
45 NopInst.addOperand(MCOperand::createReg(ARM::R0)); in getNoop()
47 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
48 NopInst.addOperand(MCOperand::createReg(0)); in getNoop()
|
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| D | SystemZDisassembler.cpp | 83 Inst.addOperand(MCOperand::createReg(RegNo)); in decodeRegisterClass()
273 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr12Operand()
283 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDAddr20Operand()
294 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr12Operand()
296 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr12Operand()
306 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDXAddr20Operand()
308 Inst.addOperand(MCOperand::createReg(Index == 0 ? 0 : Regs[Index])); in decodeBDXAddr20Operand()
318 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDLAddr12Len8Operand()
330 Inst.addOperand(MCOperand::createReg(Base == 0 ? 0 : Regs[Base])); in decodeBDVAddr12Operand()
332 Inst.addOperand(MCOperand::createReg(SystemZMC::VR128Regs[Index])); in decodeBDVAddr12Operand()
|
| /external/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 1763 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
1793 Inst.addOperand(MCOperand::createReg(getReg())); in addCCOutOperands()
1798 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
1805 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); in addRegShiftedRegOperands()
1806 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
1815 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); in addRegShiftedImmOperands()
1833 Inst.addOperand(MCOperand::createReg(*I)); in addRegListOperands()
2043 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemNoOffsetOperands()
2070 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addAlignedMemoryOperands()
2133 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addAddrMode2Operands()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/AsmParser/ |
| D | ARMAsmParser.cpp | 2016 Inst.addOperand(MCOperand::createReg(RegNum)); in addCondCodeOperands()
2046 Inst.addOperand(MCOperand::createReg(getReg())); in addCCOutOperands()
2051 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
2058 Inst.addOperand(MCOperand::createReg(RegShiftedReg.SrcReg)); in addRegShiftedRegOperands()
2059 Inst.addOperand(MCOperand::createReg(RegShiftedReg.ShiftReg)); in addRegShiftedRegOperands()
2068 Inst.addOperand(MCOperand::createReg(RegShiftedImm.SrcReg)); in addRegShiftedImmOperands()
2086 Inst.addOperand(MCOperand::createReg(*I)); in addRegListOperands()
2315 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addMemNoOffsetOperands()
2342 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addAlignedMemoryOperands()
2405 Inst.addOperand(MCOperand::createReg(Memory.BaseRegNum)); in addAddrMode2Operands()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/ |
| D | ARMGenMCPseudoLowering.inc | 23 TmpInst.addOperand(MCOperand::createReg(0));
84 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
90 TmpInst.addOperand(MCOperand::createReg(0));
92 TmpInst.addOperand(MCOperand::createReg(0));
189 TmpInst.addOperand(MCOperand::createReg(0));
208 TmpInst.addOperand(MCOperand::createReg(ARM::PC));
214 TmpInst.addOperand(MCOperand::createReg(0));
216 TmpInst.addOperand(MCOperand::createReg(0));
291 TmpInst.addOperand(MCOperand::createReg(0));
306 TmpInst.addOperand(MCOperand::createReg(0));
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 150 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
159 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
172 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
190 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
191 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
200 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
215 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRIII()
216 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRIII()
1132 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
1144 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
[all …]
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsTargetStreamer.cpp | 133 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitR()
142 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRX()
155 emitRX(Opcode, Reg0, MCOperand::createReg(Reg1), IDLoc, STI); in emitRR()
173 TmpInst.addOperand(MCOperand::createReg(Reg0)); in emitRRX()
174 TmpInst.addOperand(MCOperand::createReg(Reg1)); in emitRRX()
183 emitRRX(Opcode, Reg0, Reg1, MCOperand::createReg(Reg2), IDLoc, STI); in emitRRR()
1018 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
1030 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
1031 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
1043 TmpInst.addOperand(MCOperand::createReg(Mips::GP)); in emitDirectiveCpLoad()
[all …]
|
| /external/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 169 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
178 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
190 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
192 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
202 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/Disassembler/ |
| D | LanaiDisassembler.cpp | 168 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
177 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRiMemoryValue()
189 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
191 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeRrMemoryValue()
201 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeSplsValue()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/Disassembler/ |
| D | RISCVDisassembler.cpp | 79 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
104 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32RegisterClass()
115 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR32CRegisterClass()
140 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64RegisterClass()
151 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPR64CRegisterClass()
182 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRCRegisterClass()
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 387 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
418 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
431 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addMemOperands()
433 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); in addMemOperands()
435 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands()
449 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addSrcIdxOperands()
450 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addSrcIdxOperands()
454 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addDstIdxOperands()
464 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOffsOperands()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/AsmParser/ |
| D | X86Operand.h | 465 Inst.addOperand(MCOperand::createReg(getReg())); in addRegOperands()
473 Inst.addOperand(MCOperand::createReg(RegNo)); in addGR32orGR64Operands()
488 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addMemOperands()
490 Inst.addOperand(MCOperand::createReg(getMemIndexReg())); in addMemOperands()
492 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOperands()
506 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addSrcIdxOperands()
507 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addSrcIdxOperands()
512 Inst.addOperand(MCOperand::createReg(getMemBaseReg())); in addDstIdxOperands()
522 Inst.addOperand(MCOperand::createReg(getMemSegReg())); in addMemOffsOperands()
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/ |
| D | MipsGenMCPseudoLowering.inc | 67 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
69 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
81 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
93 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
200 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
202 TmpInst.addOperand(MCOperand::createReg(Mips::ZERO));
246 TmpInst.addOperand(MCOperand::createReg(Mips::RA));
258 TmpInst.addOperand(MCOperand::createReg(Mips::RA_64));
270 TmpInst.addOperand(MCOperand::createReg(Mips::RA));
282 TmpInst.addOperand(MCOperand::createReg(Mips::RA));
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/Disassembler/ |
| D | PPCDisassembler.cpp | 244 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); in decodeRegisterClass()
391 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIOperands()
398 Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base])); in decodeMemRIOperands()
403 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIOperands()
419 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIXOperands()
421 Inst.insert(Inst.begin(), MCOperand::createReg(GP0Regs[Base])); in decodeMemRIXOperands()
424 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIXOperands()
439 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeMemRIX16Operands()
454 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeSPE8Operands()
469 Inst.addOperand(MCOperand::createReg(GP0Regs[Base])); in decodeSPE4Operands()
[all …]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/Disassembler/ |
| D | BPFDisassembler.cpp | 110 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPRRegisterClass()
125 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeGPR32RegisterClass()
132 Inst.addOperand(MCOperand::createReg(GPRDecoderTable[Register])); in decodeMemoryOpValue()
213 Instr.addOperand(MCOperand::createReg(BPF::R6)); in getInstruction()
|
| /external/llvm/lib/Target/Sparc/Disassembler/ |
| D | SparcDisassembler.cpp | 159 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeIntRegsRegisterClass()
170 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeI64RegsRegisterClass()
182 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeFPRegsRegisterClass()
194 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeDFPRegsRegisterClass()
209 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeQFPRegsRegisterClass()
220 Inst.addOperand(MCOperand::createReg(Reg)); in DecodeCPRegsRegisterClass()
229 Inst.addOperand(MCOperand::createReg(FCCRegDecoderTable[RegNo])); in DecodeFCCRegsRegisterClass()
238 Inst.addOperand(MCOperand::createReg(ASRRegDecoderTable[RegNo])); in DecodeASRRegsRegisterClass()
247 Inst.addOperand(MCOperand::createReg(PRRegDecoderTable[RegNo])); in DecodePRRegsRegisterClass()
262 Inst.addOperand(MCOperand::createReg(RegisterPair)); in DecodeIntPairRegisterClass()
[all …]
|