Home
last modified time | relevance | path

Searched refs:csel (Results 1 – 25 of 150) sorted by relevance

123456

/external/libhevc/common/arm64/
Dihevc_intra_pred_luma_mode_18_34.s125 csel x0, x20, x0,ne
127 csel x6, x20, x6,eq
129 csel x6, x20, x6,ne
153 csel x0, x20, x0,ne
154 csel x8, x0, x8,ne
164 csel x2, x20, x2,ne
178 csel x2, x20, x2,eq
182 csel x12, x4, x12,eq
189 csel x0, x20, x0,eq
190 csel x11, x4, x11,eq
[all …]
Dihevc_sao_edge_offset_class2_chroma.s143 csel x12, x20, x12,LT
147 csel x12, x20, x12,GT //SIGN(pu1_src[0] - pu1_src_top_left[0])
151 csel x11, x20, x11,LT
155 csel x11, x20, x11,GT //SIGN(pu1_src[0] - pu1_src[2 + src_strd])
167 …csel x9, x20, x9, ge //u1_pos_0_0_tmp_u = CLIP3(pu1_src[0] + pi1_sao_offset[edg…
170 …csel x9, x20, x9, LT //u1_pos_0_0_tmp_u = CLIP3(pu1_src[0] + pi1_sao_offset[edg…
182 csel x12, x20, x12,LT
185 csel x12, x20, x12,GT //SIGN(pu1_src[0] - pu1_src_top_left[0])
189 csel x11, x20, x11,LT
193 csel x11, x20, x11,GT //SIGN(pu1_src[0] - pu1_src[3 + src_strd])
[all …]
Dihevc_sao_edge_offset_class3_chroma.s138 csel x12, x20, x12,LT
140 csel x12, x20, x12,GT //SIGN(pu1_src[wd - 2] - pu1_src_top_right[0])
147 csel x11, x20, x11,LT
149 csel x11, x20, x11,GT //SIGN(pu1_src[wd - 2] - pu1_src[wd - 2 - 2 + src_strd])
162 …csel x9, x20, x9, ge //u1_pos_0_0_tmp_u = CLIP3(pu1_src[wd - 2] + pi1_sao_offse…
165 …csel x9, x20, x9, LT //u1_pos_0_0_tmp_u = CLIP3(pu1_src[wd - 2] + pi1_sao_offse…
174 csel x12, x20, x12,LT
176 csel x12, x20, x12,GT //SIGN(pu1_src[wd - 1] - pu1_src_top_right[1])
183 csel x11, x20, x11,LT
185 csel x11, x20, x11,GT //SIGN(pu1_src[wd - 1] - pu1_src[wd - 1 - 2 + src_strd])
[all …]
Dihevc_sao_edge_offset_class2.s126 csel x12, x20, x12,LT
128 csel x12, x20, x12,GT //SIGN(pu1_src[0] - pu1_src_top_left[0])
135 csel x11, x20, x11,LT
137 csel x11, x20, x11,GT //SIGN(pu1_src[0] - pu1_src[1 + src_strd])
148 …csel x9, x20, x9, ge //u1_pos_0_0_tmp = CLIP3(pu1_src[0] + pi1_sao_offset[edge_…
151 …csel x9, x20, x9, LT //u1_pos_0_0_tmp = CLIP3(pu1_src[0] + pi1_sao_offset[edge_…
173 csel x11, x20, x11,LT
175 …csel x11, x20, x11,GT //SIGN(pu1_src[wd - 1 + (ht - 1) * src_strd] - pu1_src[wd …
179 csel x4, x20, x4,LT
181 …csel x4, x20, x4,GT //SIGN(pu1_src[wd - 1 + (ht - 1) * src_strd] - pu1_src[wd …
[all …]
Dihevc_sao_edge_offset_class3.s131 csel x12, x20, x12,LT
135 csel x12, x20, x12,GT //SIGN(pu1_src[wd - 1] - pu1_src_top_right[0])
138 csel x11, x20, x11,LT
140 csel x11, x20, x11,GT //SIGN(pu1_src[wd - 1] - pu1_src[wd - 1 - 1 + src_strd])
153 …csel x9, x20, x9, ge //u1_pos_0_0_tmp = CLIP3(pu1_src[0] + pi1_sao_offset[edge_…
156 …csel x9, x20, x9, LT //u1_pos_0_0_tmp = CLIP3(pu1_src[0] + pi1_sao_offset[edge_…
180 csel x11, x20, x11,LT
182 …csel x11, x20, x11,GT //SIGN(pu1_src[(ht - 1) * src_strd] - pu1_src[(ht - 1) * s…
186 csel x14, x20, x14,LT
188 … csel x14, x20, x14,GT //SIGN(pu1_src[(ht - 1) * src_strd] - pu1_src_bot_left[0])
[all …]
Dihevc_deblk_chroma_horz.s93 csel x1, x20, x1,gt
103 csel x2, x20, x2,gt
110 csel x1, x20, x1,gt
116 csel x1, x20, x1,pl
118 csel x1, x20, x1,mi
129 csel x2, x20, x2,gt
133 csel x2, x20, x2,pl
135 csel x2, x20, x2,mi
Dihevc_intra_pred_chroma_mode_18_34.s125 csel x0, x20, x0,ne
127 csel x6, x20, x6,eq
129 csel x6, x20, x6,ne
169 csel x0, x20, x0,ne
172 csel x8, x20, x8,eq
174 csel x8, x20, x8,ne
Dihevc_intra_pred_luma_mode2.s169 csel x2, x20, x2,gt
173 csel x11, x4, x11,le
178 csel x2, x20, x2,le
187 csel x2, x20, x2,le
192 csel x2, x20, x2,le
202 csel x0, x20, x0,le
209 csel x0, x20, x0,le
212 csel x12, x4, x12,le
Dihevc_deblk_chroma_vert.s101 csel x3, x20, x3,gt
117 csel x2, x20, x2,gt
130 csel x3, x20, x3,gt
134 csel x3, x20, x3,pl
136 csel x3, x20, x3,mi
150 csel x2, x20, x2,gt
154 csel x2, x20, x2,pl
156 csel x2, x20, x2,mi
Dihevc_intra_pred_luma_planar.s317 csel x12, x20, x12,gt
319 csel x14, x20, x14,gt
320 csel x1, x4, x1,le //nt reloaded (refresh the value)
322 csel x12, x20, x12,le
324 csel x14, x0, x14,le //x14 reset
328 csel x6, x20, x6,le
332 csel x5, x20, x5,le
369 csel x2, x20, x2,gt
373 csel x2, x20, x2,le
385 csel x1, x4, x1,le //nt reloaded (refresh the value) (cond loop)
[all …]
Dihevc_deblk_luma_horz.s71 csel x7, x20, x7,gt
75 csel x7, x20, x7,lt // x7 has the beta_index value
83 csel x3, x20, x3,gt
87 csel x3, x20, x3,lt // x3 has the tc_index value
334 csel x9, x20, x9,eq
336 csel x10, x20, x10,eq
351 csel x9, x20, x9,gt
353 csel x9, x20, x9,le
362 csel x10, x20, x10,gt
364 csel x10, x20, x10,le
[all …]
Dihevc_intra_pred_chroma_mode_3_to_9.s277 csel x8, x20, x8,gt
279 csel x2, x20, x2,gt
280 csel x8, x12, x8,le
282 csel x2, x20, x2,le
284 csel x2, x20, x2,le
286 csel x11,x20,x11,le
292 csel x0, x20, x0,le
328 csel x0, x20, x0,le
331 csel x8, x20, x8,gt
341 csel x8, x12, x8,le
[all …]
Dihevc_intra_pred_chroma_mode_27_to_33.s262 csel x8, x20, x8,gt
265 csel x4, x20, x4,gt
291 csel x6, x20, x6,le
322 csel x4, x5, x4,le //reload nt
397 csel x8, x1, x8,le //reload the source to pu1_src+2nt
402 csel x8, x20, x8,gt
410 csel x12,x20,x12,le
415 csel x12, x20, x12,le
420 csel x2, x20, x2,le
456 csel x10, x20, x10,gt
[all …]
Dihevc_intra_pred_luma_mode_27_to_33.s267 csel x8, x20, x8,gt
270 csel x7, x20, x7,gt
296 csel x6, x20, x6,le
328 csel x4, x5, x4,le //reload nt
403 csel x8, x1, x8,le //reload the source to pu1_src+2nt
408 csel x8, x20, x8,gt
416 csel x12,x20,x12,le
421 csel x12, x20, x12,le
426 csel x2, x20, x2,le
461 csel x10, x20, x10,gt
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/
Darm64-long-shift.ll8 ; CHECK: csel [[LO_FOR_HI:x[0-9]+]], xzr, [[LO_FOR_HI_NORMAL]], eq
14 ; CHECK: csel x1, [[HI_BIG_SHIFT]], [[HI_NORMAL]], ge
15 ; CHECK: csel x0, xzr, [[HI_BIG_SHIFT]], ge
27 ; CHECK: csel [[HI_FOR_LO:x[0-9]+]], xzr, [[HI_FOR_LO_NORMAL]], eq
33 ; CHECK: csel x0, [[LO_BIG_SHIFT]], [[LO_NORMAL]], ge
35 ; CHECK: csel x1, [[BIGSHIFT_HI]], [[LO_BIG_SHIFT]], ge
47 ; CHECK: csel [[HI_FOR_LO:x[0-9]+]], xzr, [[HI_FOR_LO_NORMAL]], eq
52 ; CHECK: csel x0, [[LO_BIG_SHIFT]], [[LO_NORMAL]], ge
53 ; CHECK: csel x1, xzr, [[LO_BIG_SHIFT]], ge
Dexpand-select.ll15 ; CHECK-NEXT: csel x11, x2, x6, ne
16 ; CHECK-NEXT: csel x12, x3, x7, ne
17 ; CHECK-NEXT: csel x9, x4, x9, ne
18 ; CHECK-NEXT: csel x10, x5, x10, ne
45 ; CHECK-NEXT: csel x11, x5, x11, ne
46 ; CHECK-NEXT: csel x9, x4, x9, ne
48 ; CHECK-NEXT: csel x10, x3, x7, ne
49 ; CHECK-NEXT: csel x12, x2, x6, ne
Dsdivpow2.ll10 ; CHECK-NEXT: csel w8, w8, w0, lt
22 ; CHECK-NEXT: csel w8, w8, w0, lt
34 ; CHECK-NEXT: csel w8, w8, w0, lt
46 ; CHECK-NEXT: csel x8, x8, x0, lt
58 ; CHECK-NEXT: csel x8, x8, x0, lt
70 ; CHECK-NEXT: csel x8, x8, x0, lt
83 ; CHECK-NEXT: csel x8, x8, x0, lt
Darm64-atomic-128.ll91 ; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
93 ; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
94 ; CHECK-DAG: csel [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2, ne
112 ; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
114 ; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
115 ; CHECK-DAG: csel [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2, ne
133 ; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
135 ; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
136 ; CHECK-DAG: csel [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2, ne
154 ; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
[all …]
Dfast-isel-sdiv.ll19 ; CHECK-NEXT: csel w8, w8, w0, lt
31 ; CHECK-NEXT: csel w8, w8, w0, lt
52 ; CHECK-NEXT: csel x8, x8, x0, lt
64 ; CHECK-NEXT: csel x8, x8, x0, lt
/external/llvm/test/CodeGen/AArch64/
Darm64-long-shift.ll9 ; CHECK: csel [[LO_FOR_HI:x[0-9]+]], xzr, [[LO_FOR_HI_NORMAL]], eq
15 ; CHECK: csel x1, [[HI_BIG_SHIFT]], [[HI_NORMAL]], ge
17 ; CHECK: csel x0, xzr, [[SMALLSHIFT_LO]], ge
30 ; CHECK: csel [[HI_FOR_LO:x[0-9]+]], xzr, [[HI_FOR_LO_NORMAL]], eq
36 ; CHECK: csel x0, [[LO_BIG_SHIFT]], [[LO_NORMAL]], ge
39 ; CHECK: csel x1, [[BIGSHIFT_HI]], [[SMALLSHIFT_HI]], ge
52 ; CHECK: csel [[HI_FOR_LO:x[0-9]+]], xzr, [[HI_FOR_LO_NORMAL]], eq
58 ; CHECK: csel x0, [[LO_BIG_SHIFT]], [[LO_NORMAL]], ge
60 ; CHECK: csel x1, xzr, [[SMALLSHIFT_HI]], ge
Dsdivpow2.ll8 ; CHECK: csel w8, w8, w0, lt
18 ; CHECK: csel w8, w8, w0, lt
28 ; CHECK: csel w8, w8, w0, lt
38 ; CHECK: csel x8, x8, x0, lt
48 ; CHECK: csel x8, x8, x0, lt
58 ; CHECK: csel x8, x8, x0, lt
69 ; CHECK: csel x8, x8, x0, lt
Darm64-atomic-128.ll91 ; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
93 ; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
94 ; CHECK-DAG: csel [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2, ne
112 ; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
114 ; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
115 ; CHECK-DAG: csel [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2, ne
133 ; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
135 ; CHECK-DAG: csel [[SCRATCH_REGHI:x[0-9]+]], [[DEST_REGHI]], x3, ne
136 ; CHECK-DAG: csel [[SCRATCH_REGLO:x[0-9]+]], [[DEST_REGLO]], x2, ne
154 ; CHECK: csel [[CMP:w[0-9]+]], [[LOCMP]], [[HICMP]], eq
[all …]
Dfast-isel-sdiv.ll15 ; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt
25 ; CHECK-NEXT: csel [[REG2:w[0-9]+]], [[REG1]], w0, lt
42 ; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt
52 ; CHECK-NEXT: csel [[REG2:x[0-9]+]], [[REG1]], x0, lt
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/
Darm64-arithmetic-encoding.s550 csel w1, w2, w3, eq
551 csel x1, x2, x3, eq
573 csel w12, w3, w23, CC
574 csel w11, w2, w22, LO
575 csel w10, w1, w21, MI
576 csel x9, x9, x1, PL
577 csel x8, x8, x2, VS
582 csel x3, x4, x7, LT
583 csel x2, x3, x8, GT
584 csel x1, x2, x9, LE
[all …]
/external/llvm/test/MC/AArch64/
Darm64-arithmetic-encoding.s550 csel w1, w2, w3, eq
551 csel x1, x2, x3, eq
573 csel w12, w3, w23, CC
574 csel w11, w2, w22, LO
575 csel w10, w1, w21, MI
576 csel x9, x9, x1, PL
577 csel x8, x8, x2, VS
582 csel x3, x4, x7, LT
583 csel x2, x3, x8, GT
584 csel x1, x2, x9, LE
[all …]

123456