1; RUN: llc -mtriple=aarch64-apple-darwin                             -verify-machineinstrs < %s | FileCheck %s
2; RUN: llc -mtriple=aarch64-apple-darwin -fast-isel -fast-isel-abort=1 -verify-machineinstrs < %s | FileCheck %s
3
4define i32 @sdiv_i32_exact(i32 %a) {
5; CHECK-LABEL: sdiv_i32_exact
6; CHECK:       asr {{w[0-9]+}}, w0, #3
7  %1 = sdiv exact i32 %a, 8
8  ret i32 %1
9}
10
11define i32 @sdiv_i32_pos(i32 %a) {
12; CHECK-LABEL: sdiv_i32_pos
13; CHECK:       add [[REG1:w[0-9]+]], w0, #7
14; CHECK-NEXT:  cmp w0, #0
15; CHECK-NEXT:  csel [[REG2:w[0-9]+]], [[REG1]], w0, lt
16; CHECK-NEXT:  asr {{w[0-9]+}}, [[REG2]], #3
17  %1 = sdiv i32 %a, 8
18  ret i32 %1
19}
20
21define i32 @sdiv_i32_neg(i32 %a) {
22; CHECK-LABEL: sdiv_i32_neg
23; CHECK:       add [[REG1:w[0-9]+]], w0, #7
24; CHECK-NEXT:  cmp w0, #0
25; CHECK-NEXT:  csel [[REG2:w[0-9]+]], [[REG1]], w0, lt
26; CHECK-NEXT:  neg {{w[0-9]+}}, [[REG2]], asr #3
27  %1 = sdiv i32 %a, -8
28  ret i32 %1
29}
30
31define i64 @sdiv_i64_exact(i64 %a) {
32; CHECK-LABEL: sdiv_i64_exact
33; CHECK:       asr {{x[0-9]+}}, x0, #4
34  %1 = sdiv exact i64 %a, 16
35  ret i64 %1
36}
37
38define i64 @sdiv_i64_pos(i64 %a) {
39; CHECK-LABEL: sdiv_i64_pos
40; CHECK:       add [[REG1:x[0-9]+]], x0, #15
41; CHECK-NEXT:  cmp x0, #0
42; CHECK-NEXT:  csel [[REG2:x[0-9]+]], [[REG1]], x0, lt
43; CHECK-NEXT:  asr {{x[0-9]+}}, [[REG2]], #4
44  %1 = sdiv i64 %a, 16
45  ret i64 %1
46}
47
48define i64 @sdiv_i64_neg(i64 %a) {
49; CHECK-LABEL: sdiv_i64_neg
50; CHECK:       add [[REG1:x[0-9]+]], x0, #15
51; CHECK-NEXT:  cmp x0, #0
52; CHECK-NEXT:  csel [[REG2:x[0-9]+]], [[REG1]], x0, lt
53; CHECK-NEXT:  neg {{x[0-9]+}}, [[REG2]], asr #4
54  %1 = sdiv i64 %a, -16
55  ret i64 %1
56}
57