| /external/libhevc/common/arm/ |
| D | ihevc_intra_pred_luma_planar.s | 152 vdup.s8 d5, r8 @row + 1
154 …vmov d7, d5 @mov #1 to d7 to used for inc for row+1 and dec for nt-1-r…
190 vmlal.u8 q6, d5, d0 @(1)(row+1) * src[nt-1]
202 vadd.s8 d5, d5, d7 @(1)
207 vmlal.u8 q15, d5, d0 @(2)
217 vadd.s8 d5, d5, d7 @(2)
221 vmlal.u8 q14, d5, d0 @(3)
234 vadd.s8 d5, d5, d7 @(3)
238 vmlal.u8 q5, d5, d0 @(4)
251 vadd.s8 d5, d5, d7 @(4)
[all …]
|
| D | ihevc_itrans_recon_16x16.s | 231 vld1.16 d5,[r9],r6
286 vmlal.s16 q6,d5,d1[2]
288 vmlsl.s16 q7,d5,d3[2]
290 vmlsl.s16 q8,d5,d0[2]
292 vmlsl.s16 q9,d5,d2[2]
311 vld1.16 d5,[r9],r6
348 vmlal.s16 q6,d5,d3[2]
356 vmlsl.s16 q7,d5,d2[2]
362 vmlal.s16 q8,d5,d1[2]
368 vmlsl.s16 q9,d5,d0[2]
[all …]
|
| D | ihevc_itrans_recon_32x32.s | 122 @d5[0]= 50 d7[0]=18
123 @d5[1]= 46 d7[1]=13
124 @d5[2]= 43 d7[2]=9
125 @d5[3]= 38 d7[3]=4
178 vld1.16 {d4,d5,d6,d7},[r14]!
225 vmlal.s16 q15,d9,d5[1] @// y1 * sin1 - y3 * sin3(part of b3)
264 vmlal.s16 q13,d15,d5[1]
273 vmlal.s16 q8,d12,d5[0]
276 vmlsl.s16 q9,d13,d5[2]
340 vmlal.s16 q15,d15,d5[3]
[all …]
|
| D | ihevc_padding.s | 138 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
139 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
140 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
141 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
142 vst1.8 {d4,d5},[r6] @128/8 = 16 bytes store
257 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
258 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
259 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
260 vst1.8 {d4,d5},[r6]! @128/8 = 16 bytes store
261 vst1.8 {d4,d5},[r6] @128/8 = 16 bytes store
[all …]
|
| D | ihevc_inter_pred_filters_luma_vert.s | 169 vld1.u8 {d5},[r3],r2 @src_tmp2 = vld1_u8(pu1_src_tmp)@
174 vmlsl.u8 q4,d5,d27 @mul_res1 = vmlsl_u8(mul_res1, src_tmp2, coeffabs_5)@
193 vmlal.u8 q5,d5,d26 @mul_res2 = vmlal_u8(mul_res2, src_tmp2, coeffabs_4)@
212 vmlal.u8 q6,d5,d25
225 vmlsl.u8 q7,d5,d24
231 vld1.u8 {d5},[r3],r2 @src_tmp2 = vld1_u8(pu1_src_tmp)@
262 vmlsl.u8 q4,d5,d27 @mul_res1 = vmlsl_u8(mul_res1, src_tmp2, coeffabs_5)@
284 vmlal.u8 q5,d5,d26 @mul_res2 = vmlal_u8(mul_res2, src_tmp2, coeffabs_4)@
307 vmlal.u8 q6,d5,d25
331 vmlsl.u8 q7,d5,d24
[all …]
|
| D | ihevc_intra_pred_luma_mode_3_to_9.s | 210 vsub.s8 d5, d9, d2 @ref_main_idx + 1 (row 1)
216 vtbl.8 d17, {d0,d1}, d5 @load from ref_main_idx + 1 (row 1)
228 vsub.s8 d5, d5, d3 @ref_main_idx + 1 (row 3)
237 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx + 1 (row 3)
250 vsub.s8 d5, d5, d3 @ref_main_idx + 1 (row 5)
259 vtbl.8 d17, {d0,d1}, d5 @load from ref_main_idx + 1 (row 5)
272 vsub.s8 d5, d5, d3 @ref_main_idx + 1 (row 7)
281 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx + 1 (row 7)
334 vtbl.8 d11, {d0,d1}, d5 @load from ref_main_idx - 1 (row 7)
354 vsub.s8 d5, d9, d2 @ref_main_idx - 1 (row 1)
[all …]
|
| /external/capstone/suite/MC/ARM/ |
| D | neon-bitwise-encoding.s.cs | 108 0x05,0x52,0xb5,0xf3 = vclt.s16 d5, d5, #0
110 0x13,0x58,0x15,0xf3 = vceq.i16 d5, d5, d3
112 0x03,0x53,0x15,0xf2 = vcgt.s16 d5, d5, d3
114 0x13,0x53,0x15,0xf2 = vcge.s16 d5, d5, d3
116 0x05,0x50,0xb5,0xf3 = vcgt.s16 d5, d5, #0
118 0x85,0x50,0xb5,0xf3 = vcge.s16 d5, d5, #0
120 0x05,0x51,0xb5,0xf3 = vceq.i16 d5, d5, #0
122 0x85,0x51,0xb5,0xf3 = vcle.s16 d5, d5, #0
123 0x3e,0x5e,0x05,0xf3 = vacge.f32 d5, d5, d30
125 0x3e,0x5e,0x25,0xf3 = vacgt.f32 d5, d5, d30
|
| D | neon-vld-encoding.s.cs | 11 0x5f,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64]
12 0x8f,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3]
15 0x5f,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64]
16 0x8f,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3]
35 0x5d,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64]!
36 0x8d,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3]!
39 0x56,0x46,0x23,0xf4 = vld1.16 {d4, d5, d6}, [r3:64], r6
40 0x86,0x56,0x23,0xf4 = vld1.32 {d5, d6, d7}, [r3], r6
43 0x5d,0x42,0x23,0xf4 = vld1.16 {d4, d5, d6, d7}, [r3:64]!
44 0x8d,0x52,0x23,0xf4 = vld1.32 {d5, d6, d7, d8}, [r3]!
[all …]
|
| D | neon-mul-encoding.s.cs | 50 0x44,0x58,0xa5,0xf2 = vmul.i32 d5, d5, d4[0]
51 0x65,0x69,0xa6,0xf2 = vmul.f32 d6, d6, d5[1]
58 0x65,0xc9,0xac,0xf3 = vmul.f32 q6, q6, d5[1]
63 0x63,0x58,0xa4,0xf2 = vmul.i32 d5, d4, d3[1]
64 0x44,0x48,0xa5,0xf2 = vmul.i32 d4, d5, d4[0]
65 0x65,0x39,0xa6,0xf2 = vmul.f32 d3, d6, d5[1]
72 0x65,0x69,0xac,0xf3 = vmul.f32 q3, q6, d5[1]
|
| /external/tcpdump/tests/ |
| D | geonet_and_calm_fast.out | 2 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
5 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
8 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
11 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
14 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
20 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
28 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
31 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
34 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
37 GeoNet src:00:0c:42:6d:54:d5; v:0 NH:0-Any HT:1-0-Beacon HopLim:1 Payload:0 GN_ADDR:00:00:00:0c:42:…
[all …]
|
| /external/libavc/common/arm/ |
| D | ih264_inter_pred_filters_luma_horz_a9q.s | 125 vld1.8 {d5, d6, d7}, [r0], r2 @// Load row1
128 vext.8 d28, d5, d6, #5 @//extract a[5] (column1,row1)
131 vaddl.u8 q7, d28, d5 @// a0 + a5 (column1,row1)
136 vext.8 d28, d5, d6, #2 @//extract a[2] (column1,row1)
144 vext.8 d28, d5, d6, #3 @//extract a[3] (column1,row1)
152 vext.8 d28, d5, d6, #1 @//extract a[1] (column1,row1)
160 vext.8 d28, d5, d6, #4 @//extract a[4] (column1,row1)
180 vld1.8 {d5, d6}, [r0], r2 @// Load row1
181 vext.8 d28, d5, d6, #5 @//extract a[5] (column1,row1)
183 vext.8 d25, d5, d6, #2 @//extract a[2] (column1,row1)
[all …]
|
| D | ih264_inter_pred_luma_horz_qpel_a9q.s | 132 vld1.8 {d5, d6, d7}, [r0], r2 @// Load row1
135 vext.8 d28, d5, d6, #5 @//extract a[5] (column1,row1)
138 vaddl.u8 q7, d28, d5 @// a0 + a5 (column1,row1)
143 vext.8 d28, d5, d6, #2 @//extract a[2] (column1,row1)
151 vext.8 d28, d5, d6, #3 @//extract a[3] (column1,row1)
159 vext.8 d28, d5, d6, #1 @//extract a[1] (column1,row1)
167 vext.8 d28, d5, d6, #4 @//extract a[4] (column1,row1)
192 vld1.8 {d5, d6}, [r0], r2 @// Load row1
193 vext.8 d28, d5, d6, #5 @//extract a[5] (column1,row1)
195 vext.8 d25, d5, d6, #2 @//extract a[2] (column1,row1)
[all …]
|
| D | ih264_inter_pred_luma_horz_hpel_vert_qpel_a9q.s | 152 vext.8 d5, d0, d1, #5
153 vaddl.u8 q3, d0, d5
164 vext.8 d5, d0, d1, #5
165 vaddl.u8 q4, d0, d5
178 vext.8 d5, d0, d1, #5
179 vaddl.u8 q5, d0, d5
192 vext.8 d5, d0, d1, #5
193 vaddl.u8 q6, d0, d5
206 vext.8 d5, d0, d1, #5
207 vaddl.u8 q7, d0, d5
[all …]
|
| /external/libvpx/libvpx/vp8/common/arm/neon/ |
| D | shortidct4x4llm_neon.c | 28 int16x4_t d2, d3, d4, d5, d10, d11, d12, d13; in vp8_short_idct4x4llm_neon() local
37 d5 = vld1_s16(input + 12); in vp8_short_idct4x4llm_neon()
41 q2s16 = vcombine_s16(d3, d5); in vp8_short_idct4x4llm_neon()
59 d5 = vqsub_s16(d12, d11); in vp8_short_idct4x4llm_neon()
62 v2tmp1 = vtrn_s32(vreinterpret_s32_s16(d3), vreinterpret_s32_s16(d5)); in vp8_short_idct4x4llm_neon()
88 d5 = vqsub_s16(d12, d11); in vp8_short_idct4x4llm_neon()
93 d5 = vrshr_n_s16(d5, 3); in vp8_short_idct4x4llm_neon()
96 v2tmp1 = vtrn_s32(vreinterpret_s32_s16(d3), vreinterpret_s32_s16(d5)); in vp8_short_idct4x4llm_neon()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/ARM/ |
| D | neon-vld-encoding.s | 12 vld1.16 {d4, d5, d6}, [r3:64]
13 vld1.32 {d5, d6, d7}, [r3]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
17 vld1.32 {d5, d6, d7, d8}, [r3]
39 vld1.16 {d4, d5, d6}, [r3:64]!
40 vld1.32 {d5, d6, d7}, [r3]!
44 vld1.16 {d4, d5, d6}, [r3:64], r6
45 vld1.32 {d5, d6, d7}, [r3], r6
49 vld1.16 {d4, d5, d6, d7}, [r3:64]!
50 vld1.32 {d5, d6, d7, d8}, [r3]!
[all …]
|
| D | basic-arm-instructions-v8.1a.s | 16 vqrdmlsh.f64 d3, d5, d5
72 vqrdmlsh.s16 d7, d6, d5
104 vqrdmlsh.f32 q3, q4, d5[1]
105 vqrdmlsh.f64 d3, d5, d5[0]
|
| D | neon-mul-encoding.s | 111 vmul.u32 d5, d4[0]
112 vmul.f32 d6, d5[1]
120 vmul.f32 q6, d5[1]
126 vmul.s32 d5, d4, d3[1]
127 vmul.u32 d4, d5, d4[0]
128 vmul.f32 d3, d6, d5[1]
136 vmul.f32 q3, q6, d5[1]
143 @ CHECK: vmul.i32 d5, d5, d4[0] @ encoding: [0x44,0x58,0xa5,0xf2]
144 @ CHECK: vmul.f32 d6, d6, d5[1] @ encoding: [0x65,0x69,0xa6,0xf2]
152 @ CHECK: vmul.f32 q6, q6, d5[1] @ encoding: [0x65,0xc9,0xac,0xf3]
[all …]
|
| /external/llvm/test/MC/ARM/ |
| D | neon-vld-encoding.s | 12 vld1.16 {d4, d5, d6}, [r3:64]
13 vld1.32 {d5, d6, d7}, [r3]
16 vld1.16 {d4, d5, d6, d7}, [r3:64]
17 vld1.32 {d5, d6, d7, d8}, [r3]
39 vld1.16 {d4, d5, d6}, [r3:64]!
40 vld1.32 {d5, d6, d7}, [r3]!
44 vld1.16 {d4, d5, d6}, [r3:64], r6
45 vld1.32 {d5, d6, d7}, [r3], r6
49 vld1.16 {d4, d5, d6, d7}, [r3:64]!
50 vld1.32 {d5, d6, d7, d8}, [r3]!
[all …]
|
| D | basic-arm-instructions-v8.1a.s | 16 vqrdmlsh.f64 d3, d5, d5
72 vqrdmlsh.s16 d7, d6, d5
103 vqrdmlsh.f32 q3, q4, d5[1]
104 vqrdmlsh.f64 d3, d5, d5[0]
|
| D | neon-mul-encoding.s | 111 vmul.u32 d5, d4[0]
112 vmul.f32 d6, d5[1]
120 vmul.f32 q6, d5[1]
126 vmul.s32 d5, d4, d3[1]
127 vmul.u32 d4, d5, d4[0]
128 vmul.f32 d3, d6, d5[1]
136 vmul.f32 q3, q6, d5[1]
143 @ CHECK: vmul.i32 d5, d5, d4[0] @ encoding: [0x44,0x58,0xa5,0xf2]
144 @ CHECK: vmul.f32 d6, d6, d5[1] @ encoding: [0x65,0x69,0xa6,0xf2]
152 @ CHECK: vmul.f32 q6, q6, d5[1] @ encoding: [0x65,0xc9,0xac,0xf3]
[all …]
|
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| D | loopfilter_8_neon.asm | 46 vld1.u8 {d5}, [r3@64], r1 ; p1
63 vst1.u8 {d5}, [r3@64], r1 ; store oq2
125 vld1.u8 {d5}, [r2], r1
135 vtrn.32 d5, d17
138 vtrn.16 d3, d5
144 vtrn.8 d5, d6
164 vst2.8 {d4[0], d5[0]}, [r3], r1
165 vst2.8 {d4[1], d5[1]}, [r3], r1
166 vst2.8 {d4[2], d5[2]}, [r3], r1
167 vst2.8 {d4[3], d5[3]}, [r3], r1
[all …]
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| /external/python/cpython2/Tools/pybench/ |
| D | Dict.py | 17 d5 = {}
23 d5 = {6:7,8:9,10:11}
29 d5 = {}
35 d5 = {6:7,8:9,10:11}
41 d5 = {}
47 d5 = {6:7,8:9,10:11}
53 d5 = {}
59 d5 = {6:7,8:9,10:11}
65 d5 = {}
71 d5 = {6:7,8:9,10:11}
|
| /external/libpng/arm/ |
| D | filter_neon.S | 69 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
71 vadd.u8 d1, d0, d5
89 vext.8 d5, d22, d23, #3
92 vadd.u8 d1, d0, d5
124 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
129 vadd.u8 d1, d1, d5
151 vext.8 d5, d22, d23, #3
158 vadd.u8 d1, d1, d5
197 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
202 vadd.u8 d1, d1, d5
[all …]
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| /external/pdfium/third_party/libpng16/arm/ |
| D | filter_neon.S | 69 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
71 vadd.u8 d1, d0, d5
89 vext.8 d5, d22, d23, #3
92 vadd.u8 d1, d0, d5
124 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
129 vadd.u8 d1, d1, d5
151 vext.8 d5, d22, d23, #3
158 vadd.u8 d1, d1, d5
197 vld4.32 {d4[],d5[],d6[],d7[]}, [r1,:128]
202 vadd.u8 d1, d1, d5
[all …]
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| /external/libvpx/config/arm-neon/vpx_dsp/arm/ |
| D | loopfilter_8_neon.asm.S | 56 vld1.u8 {d5}, [r3,:64], r1 @ p1
73 vst1.u8 {d5}, [r3,:64], r1 @ store oq2
137 vld1.u8 {d5}, [r2], r1
147 vtrn.32 d5, d17
150 vtrn.16 d3, d5
156 vtrn.8 d5, d6
176 vst2.8 {d4[0], d5[0]}, [r3], r1
177 vst2.8 {d4[1], d5[1]}, [r3], r1
178 vst2.8 {d4[2], d5[2]}, [r3], r1
179 vst2.8 {d4[3], d5[3]}, [r3], r1
[all …]
|