1//RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8.1a -mattr=neon -show-encoding < %s 2>%t | FileCheck %s --check-prefix=CHECK-V81aTHUMB
2//RUN: FileCheck --check-prefix=CHECK-ERROR <%t %s
3//RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8.1a -mattr=neon -show-encoding < %s 2>%t | FileCheck %s --check-prefix=CHECK-V81aARM
4//RUN: FileCheck --check-prefix=CHECK-ERROR <%t %s
5
6//RUN: not llvm-mc -triple thumb-none-linux-gnu -mattr=+v8 -mattr=neon -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
7//RUN: not llvm-mc -triple arm-none-linux-gnu -mattr=+v8 -mattr=neon -show-encoding < %s 2>&1 | FileCheck %s --check-prefix=CHECK-V8
8
9
10  .text
11//CHECK-V8THUMB: .text
12
13  vqrdmlah.i8   q0, q1, q2
14  vqrdmlah.u16  d0, d1, d2
15  vqrdmlsh.f32  q3, q4, q5
16  vqrdmlsh.f64  d3, d5, d5
17
18//CHECK-ERROR: error: invalid operand for instruction
19//CHECK-ERROR:   vqrdmlah.i8   q0, q1, q2
20//CHECK-ERROR:           ^
21//CHECK-ERROR: error: invalid operand for instruction
22//CHECK-ERROR:   vqrdmlah.u16  d0, d1, d2
23//CHECK-ERROR:           ^
24//CHECK-ERROR: error: invalid operand for instruction
25//CHECK-ERROR:   vqrdmlsh.f32  q3, q4, q5
26//CHECK-ERROR:           ^
27//CHECK-ERROR: error: invalid operand for instruction
28//CHECK-ERROR:   vqrdmlsh.f64  d3, d5, d5
29//CHECK-ERROR:           ^
30//CHECK-V8: error: invalid instruction
31//CHECK-V8:   vqrdmlah.i8   q0, q1, q2
32//CHECK-V8:   ^
33//CHECK-V8: error: invalid instruction
34//CHECK-V8:   vqrdmlah.u16  d0, d1, d2
35//CHECK-V8:   ^
36//CHECK-V8: error: invalid instruction
37//CHECK-V8:   vqrdmlsh.f32  q3, q4, q5
38//CHECK-V8:   ^
39//CHECK-V8: error: invalid instruction
40//CHECK-V8:  vqrdmlsh.f64  d3, d5, d5
41//CHECK-V8:  ^
42
43  vqrdmlah.s16    d0, d1, d2
44//CHECK-V81aARM:   vqrdmlah.s16  d0, d1, d2      @ encoding: [0x12,0x0b,0x11,0xf3]
45//CHECK-V81aTHUMB: vqrdmlah.s16  d0, d1, d2      @ encoding: [0x11,0xff,0x12,0x0b]
46//CHECK-V8: error: instruction requires: armv8.1a
47//CHECK-V8:  vqrdmlah.s16    d0, d1, d2
48//CHECK-V8:  ^
49
50  vqrdmlah.s32  d0, d1, d2
51//CHECK-V81aARM:   vqrdmlah.s32  d0, d1, d2      @ encoding: [0x12,0x0b,0x21,0xf3]
52//CHECK-V81aTHUMB: vqrdmlah.s32  d0, d1, d2      @ encoding: [0x21,0xff,0x12,0x0b]
53//CHECK-V8: error: instruction requires: armv8.1a
54//CHECK-V8:  vqrdmlah.s32  d0, d1, d2
55//CHECK-V8:  ^
56
57  vqrdmlah.s16  q0, q1, q2
58//CHECK-V81aARM:   vqrdmlah.s16  q0, q1, q2      @ encoding: [0x54,0x0b,0x12,0xf3]
59//CHECK-V81aTHUMB: vqrdmlah.s16  q0, q1, q2      @ encoding: [0x12,0xff,0x54,0x0b]
60//CHECK-V8: error: instruction requires: armv8.1a
61//CHECK-V8:  vqrdmlah.s16  q0, q1, q2
62//CHECK-V8:  ^
63
64  vqrdmlah.s32  q2, q3, q0
65//CHECK-V81aARM:   vqrdmlah.s32  q2, q3, q0      @ encoding: [0x50,0x4b,0x26,0xf3]
66//CHECK-V81aTHUMB: vqrdmlah.s32  q2, q3, q0      @ encoding: [0x26,0xff,0x50,0x4b]
67//CHECK-V8: error: instruction requires: armv8.1a
68//CHECK-V8:  vqrdmlah.s32  q2, q3, q0
69//CHECK-V8:  ^
70
71
72  vqrdmlsh.s16  d7, d6, d5
73//CHECK-V81aARM:   vqrdmlsh.s16  d7, d6, d5      @ encoding: [0x15,0x7c,0x16,0xf3]
74//CHECK-V81aTHUMB: vqrdmlsh.s16  d7, d6, d5      @ encoding: [0x16,0xff,0x15,0x7c]
75//CHECK-V8: error: instruction requires: armv8.1a
76//CHECK-V8:  vqrdmlsh.s16  d7, d6, d5
77//CHECK-V8:  ^
78
79  vqrdmlsh.s32  d0, d1, d2
80//CHECK-V81aARM:   vqrdmlsh.s32  d0, d1, d2      @ encoding: [0x12,0x0c,0x21,0xf3]
81//CHECK-V81aTHUMB: vqrdmlsh.s32  d0, d1, d2      @ encoding: [0x21,0xff,0x12,0x0c]
82//CHECK-V8: error: instruction requires: armv8.1a
83//CHECK-V8:  vqrdmlsh.s32  d0, d1, d2
84//CHECK-V8:  ^
85
86  vqrdmlsh.s16  q0, q1, q2
87//CHECK-V81aARM:   vqrdmlsh.s16  q0, q1, q2      @ encoding: [0x54,0x0c,0x12,0xf3]
88//CHECK-V81aTHUMB: vqrdmlsh.s16  q0, q1, q2      @ encoding: [0x12,0xff,0x54,0x0c]
89//CHECK-V8: error: instruction requires: armv8.1a
90//CHECK-V8:  vqrdmlsh.s16  q0, q1, q2
91//CHECK-V8:  ^
92
93  vqrdmlsh.s32    q3, q4, q5
94//CHECK-V81aARM:   vqrdmlsh.s32  q3, q4, q5      @ encoding: [0x5a,0x6c,0x28,0xf3]
95//CHECK-V81aTHUMB: vqrdmlsh.s32  q3, q4, q5      @ encoding: [0x28,0xff,0x5a,0x6c]
96//CHECK-V8: error: instruction requires: armv8.1a
97//CHECK-V8:  vqrdmlsh.s32  q3, q4, q5
98//CHECK-V8:  ^
99
100
101  vqrdmlah.i8   q0, q1, d9[0]
102  vqrdmlah.s32  q0, q1, d9[7]
103  vqrdmlah.u16  d0, d1, d2[3]
104  vqrdmlsh.f32  q3, q4, d5[1]
105  vqrdmlsh.f64  d3, d5, d5[0]
106
107//CHECK-ERROR: error: invalid operand for instruction
108//CHECK-ERROR:   vqrdmlah.i8   q0, q1, d9[0]
109//CHECK-ERROR:           ^
110//CHECK-ERROR: error: invalid operand for instruction
111//CHECK-ERROR:   vqrdmlah.s32  q0, q1, d9[7]
112//CHECK-ERROR:                            ^
113//CHECK-ERROR: error: invalid operand for instruction
114//CHECK-ERROR:   vqrdmlah.u16  d0, d1, d2[3]
115//CHECK-ERROR:           ^
116//CHECK-ERROR: error: invalid operand for instruction
117//CHECK-ERROR:   vqrdmlsh.f32  q3, q4, d5[1]
118//CHECK-ERROR:           ^
119//CHECK-ERROR: error: invalid operand for instruction
120//CHECK-ERROR:   vqrdmlsh.f64  d3, d5, d5[0]
121//CHECK-ERROR:           ^
122
123  vqrdmlah.s16  d0, d1, d2[0]
124//CHECK-V81aARM:   vqrdmlah.s16 d0, d1, d2[0]    @ encoding: [0x42,0x0e,0x91,0xf2]
125//CHECK-V81aTHUMB: vqrdmlah.s16  d0, d1, d2[0]   @ encoding: [0x91,0xef,0x42,0x0e]
126//CHECK-V8: error: instruction requires: armv8.1a
127//CHECK-V8:  vqrdmlah.s16  d0, d1, d2[0]
128//CHECK-V8:  ^
129
130  vqrdmlah.s32  d0, d1, d2[0]
131//CHECK-V81aARM:   vqrdmlah.s32 d0, d1, d2[0]    @ encoding: [0x42,0x0e,0xa1,0xf2]
132//CHECK-V81aTHUMB: vqrdmlah.s32  d0, d1, d2[0]   @ encoding: [0xa1,0xef,0x42,0x0e]
133//CHECK-V8: error: instruction requires: armv8.1a
134//CHECK-V8:  vqrdmlah.s32  d0, d1, d2[0]
135//CHECK-V8:  ^
136
137  vqrdmlah.s16  q0, q1, d2[0]
138//CHECK-V81aARM:   vqrdmlah.s16  q0, q1, d2[0]   @ encoding: [0x42,0x0e,0x92,0xf3]
139//CHECK-V81aTHUMB: vqrdmlah.s16  q0, q1, d2[0]   @ encoding: [0x92,0xff,0x42,0x0e]
140//CHECK-V8: error: instruction requires: armv8.1a
141//CHECK-V8:  vqrdmlah.s16  q0, q1, d2[0]
142//CHECK-V8:  ^
143
144  vqrdmlah.s32  q0, q1, d2[0]
145//CHECK-V81aARM:   vqrdmlah.s32  q0, q1, d2[0]   @ encoding: [0x42,0x0e,0xa2,0xf3]
146//CHECK-V81aTHUMB: vqrdmlah.s32  q0, q1, d2[0]   @ encoding: [0xa2,0xff,0x42,0x0e]
147//CHECK-V8: error: instruction requires: armv8.1a
148//CHECK-V8:  vqrdmlah.s32  q0, q1, d2[0]
149//CHECK-V8:  ^
150
151
152  vqrdmlsh.s16  d0, d1, d2[0]
153//CHECK-V81aARM:   vqrdmlsh.s16 d0, d1, d2[0]    @ encoding: [0x42,0x0f,0x91,0xf2]
154//CHECK-V81aTHUMB: vqrdmlsh.s16  d0, d1, d2[0]   @ encoding: [0x91,0xef,0x42,0x0f]
155//CHECK-V8: error: instruction requires: armv8.1a
156//CHECK-V8:  vqrdmlsh.s16  d0, d1, d2[0]
157//CHECK-V8:  ^
158
159  vqrdmlsh.s32  d0, d1, d2[0]
160//CHECK-V81aARM:   vqrdmlsh.s32 d0, d1, d2[0]    @ encoding: [0x42,0x0f,0xa1,0xf2]
161//CHECK-V81aTHUMB: vqrdmlsh.s32  d0, d1, d2[0]   @ encoding: [0xa1,0xef,0x42,0x0f]
162//CHECK-V8: error: instruction requires: armv8.1a
163//CHECK-V8:  vqrdmlsh.s32  d0, d1, d2[0]
164//CHECK-V8:  ^
165
166  vqrdmlsh.s16  q0, q1, d2[0]
167//CHECK-V81aARM:   vqrdmlsh.s16 q0, q1, d2[0]    @ encoding: [0x42,0x0f,0x92,0xf3]
168//CHECK-V81aTHUMB: vqrdmlsh.s16  q0, q1, d2[0]   @ encoding: [0x92,0xff,0x42,0x0f]
169//CHECK-V8: error: instruction requires: armv8.1a
170//CHECK-V8:  vqrdmlsh.s16  q0, q1, d2[0]
171//CHECK-V8:  ^
172
173  vqrdmlsh.s32  q0, q1, d2[0]
174//CHECK-V81aARM:   vqrdmlsh.s32 q0, q1, d2[0]    @ encoding: [0x42,0x0f,0xa2,0xf3]
175//CHECK-V81aTHUMB: vqrdmlsh.s32  q0, q1, d2[0]   @ encoding: [0xa2,0xff,0x42,0x0f]
176//CHECK-V8: error: instruction requires: armv8.1a
177//CHECK-V8:  vqrdmlsh.s32  q0, q1, d2[0]
178//CHECK-V8:  ^
179
180  setpan  #0
181//CHECK-V81aTHUMB:  setpan  #0                @       encoding: [0x10,0xb6]
182//CHECK-V81aARM:    setpan  #0                @       encoding: [0x00,0x00,0x10,0xf1]
183//CHECK-V8: instruction requires: armv8.1a
184//CHECK-V8:  setpan  #0
185//CHECK-V8:  ^
186
187  setpan  #1
188//CHECK-V81aTHUMB:  setpan  #1                @       encoding: [0x18,0xb6]
189//CHECK-V81aARM:    setpan  #1                @       encoding: [0x00,0x02,0x10,0xf1]
190//CHECK-V8: instruction requires: armv8.1a
191//CHECK-V8:  setpan  #1
192//CHECK-V8:  ^
193  setpan
194  setpan #-1
195  setpan #2
196//CHECK-ERROR: error: too few operands for instruction
197//CHECK-ERROR:  setpan
198//CHECK-ERROR:  ^
199//CHECK-ERROR: error: operand must be an immediate in the range [0,1]
200//CHECK-ERROR:  setpan #-1
201//CHECK-ERROR:         ^
202//CHECK-ERROR: error: operand must be an immediate in the range [0,1]
203//CHECK-ERROR:  setpan #2
204//CHECK-ERROR:         ^
205
206  it eq
207  setpaneq #0
208//CHECK-THUMB-ERROR: error: instruction 'setpan' is not predicable, but condition code specified
209//CHECK-THUMB-ERROR:  setpaneq #0
210//CHECK-THUMB-ERROR:  ^
211