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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dfneg-combines.ll26 %fneg = fsub float -0.000000e+00, %add
27 store float %fneg, float addrspace(1)* %out.gep
47 %fneg = fsub float -0.000000e+00, %add
48 store volatile float %fneg, float addrspace(1)* %out
74 %fneg = fsub float -0.000000e+00, %add
76 store volatile float %fneg, float addrspace(1)* %out
98 %fneg.a = fsub float -0.000000e+00, %a
99 %add = fadd float %fneg.a, %b
100 %fneg = fsub float -0.000000e+00, %add
101 store volatile float %fneg, float addrspace(1)* %out
[all …]
Dselect-fabs-fneg-extract.ll254 %fneg.x = fsub float -0.0, %x
255 %fneg.y = fsub float -0.0, %y
256 %select = select i1 %cmp, float %fneg.x, float %fneg.y
277 %fneg.x = fsub float -0.0, %x
278 %fneg.y = fsub float -0.0, %y
279 %select = select i1 %cmp, float %fneg.x, float %fneg.y
281 %add1 = fadd float %fneg.x, %w
303 %fneg.x = fsub float -0.0, %x
304 %fneg.y = fsub float -0.0, %y
305 %select = select i1 %cmp, float %fneg.x, float %fneg.y
[all …]
Dfmin_fmax_legacy.amdgcn.ll10 %fneg.a = fsub float -0.0, %a
12 %min.a = select i1 %cmp.a, float %fneg.a, float -1.0
20 %fneg.a = fsub float -0.0, %a
22 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0
30 %fneg.a = fsub float -0.0, %a
32 %min.a = select i1 %cmp.a, float %fneg.a, float -1.0
40 %fneg.a = fsub float -0.0, %a
42 %min.a = select i1 %cmp.a, float %fneg.a, float 1.0
Dfneg.f16.ll8 %fneg = fsub half -0.0, %in
9 store half %fneg, half addrspace(1)* %out
26 %fneg = fsub half -0.0, %val
27 store half %fneg, half addrspace(1)* %gep.out
65 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %in
66 store <2 x half> %fneg, <2 x half> addrspace(1)* %out
75 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %in.bc
76 store <2 x half> %fneg, <2 x half> addrspace(1)* %out
88 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %val
89 store <2 x half> %fneg, <2 x half> addrspace(1)* %gep.out
[all …]
Dfneg.f64.ll7 %fneg = fsub double -0.000000e+00, %in
8 store double %fneg, double addrspace(1)* %out
16 %fneg = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %in
17 store <2 x double> %fneg, <2 x double> addrspace(1)* %out
32 …%fneg = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, doubl…
33 store <4 x double> %fneg, <4 x double> addrspace(1)* %out
38 ; (fneg (f64 bitcast (i64 a))) => (f64 bitcast (xor (i64 a), 0x80000000))
Dselect-fabs-fneg-extract-legacy.ll4 ; Don't fold if fneg can fold into the source
19 %fneg = fsub float -0.0, %rcp
20 %select = select i1 %cmp, float %fneg, float 2.0
36 %fneg = fsub float -0.0, %mul
37 %select = select i1 %cmp, float %fneg, float 2.0
Dfneg.ll10 %fneg = fsub float -0.000000e+00, %in
11 store float %fneg, float addrspace(1)* %out
22 %fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
23 store <2 x float> %fneg, <2 x float> addrspace(1)* %out
38 …%fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.…
39 store <4 x float> %fneg, <4 x float> addrspace(1)* %out
44 ; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
Dfneg-fabs.f16.ll81 %fneg.fabs = fsub <2 x half> <half -0.0, half -0.0>, %fabs
82 store <2 x half> %fneg.fabs, <2 x half> addrspace(1)* %out
94 %fneg.fabs = fsub <2 x half> <half -0.0, half -0.0>, %fabs
95 store <2 x half> %fneg.fabs, <2 x half> addrspace(1)* %out
127 %fneg.fabs = fsub <2 x half> <half -0.0, half -0.0>, %fabs
128 %mul = fmul <2 x half> %fneg.fabs, <half 4.0, half 4.0>
142 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %fabs
144 store <2 x half> %fneg, <2 x half> addrspace(1)* %out1
153 %fneg = fsub <2 x half> <half -0.0, half -0.0>, %fabs
154 %mul = fmul <2 x half> %fneg, <half 4.0, half 4.0>
Dllvm.amdgcn.fmed3.ll15 %src0.fneg = fsub float -0.0, %src0
18 %src2.fneg.fabs = fsub float -0.0, %src2.fabs
19 …%mad = call float @llvm.amdgcn.fmed3.f32(float %src0.fneg, float %src1.fabs, float %src2.fneg.fabs)
Dcommute_modifiers.ll30 %x.fneg.fabs = fsub float -0.000000e+00, %x.fabs
31 %z = fmul float 4.0, %x.fneg.fabs
44 %x.fneg = fsub float -0.000000e+00, %x
45 %z = fmul float 4.0, %x.fneg
94 %y.fneg = fsub float -0.000000e+00, %y
95 %z = fmul float %x, %y.fneg
112 %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
113 %z = fmul float %x, %y.fabs.fneg
150 %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
151 %z = fmul float %x.fabs, %y.fabs.fneg
Dllvm.amdgcn.fmed3.f16.ll26 %src0.fneg = fsub half -0.0, %src0
29 %src2.fneg.fabs = fsub half -0.0, %src2.fabs
30 %mad = call half @llvm.amdgcn.fmed3.f16(half %src0.fneg, half %src1.fabs, half %src2.fneg.fabs)
Dllvm.amdgcn.frexp.exp.ll30 %fneg.fabs.src = fsub float -0.0, %fabs.src
31 %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f32(float %fneg.fabs.src)
57 %fneg.fabs.src = fsub double -0.0, %fabs.src
58 %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.i32.f64(double %fneg.fabs.src)
Dllvm.amdgcn.frexp.mant.ll30 %fneg.fabs.src = fsub float -0.0, %fabs.src
31 %frexp.mant = call float @llvm.amdgcn.frexp.mant.f32(float %fneg.fabs.src)
57 %fneg.fabs.src = fsub double -0.0, %fabs.src
58 %frexp.mant = call double @llvm.amdgcn.frexp.mant.f64(double %fneg.fabs.src)
Dcvt_rpi_i32_f32.ll41 %x.fneg = fsub float -0.000000e+00, %x
42 %fadd = fadd float %x.fneg, 0.5
60 %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
61 %fadd = fadd float %x.fabs.fneg, 0.5
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/SVE/
Dfneg.s10 fneg z31.h, p7/m, z31.h label
16 fneg z31.s, p7/m, z31.s label
22 fneg z31.d, p7/m, z31.d label
38 fneg z4.d, p7/m, z31.d label
50 fneg z4.d, p7/m, z31.d label
Dfneg-diagnostics.s6 fneg z31.h, p8/m, z31.h label
15 fneg z31.b, p7/m, z31.b label
20 fneg z31.h, p7/m, z31.s label
/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/
Dfma.ll16 %x.fneg = fsub float -0.0, %x
17 %y.fneg = fsub float -0.0, %y
18 %fma = call float @llvm.fma.f32(float %x.fneg, float %y.fneg, float %z)
49 %x.fneg = fsub float -0.0, %x
50 %y.fneg = fsub float -0.0, %y
51 %fma = call fast float @llvm.fma.f32(float %x.fneg, float %y.fneg, float %z)
60 %y.fneg = fsub float -0.0, %y
61 …loat -0.0, float bitcast (i32 ptrtoint (i32* @external to i32) to float)), float %y.fneg, float %z)
70 %x.fneg = fsub float -0.0, %x
71 …%fma = call float @llvm.fma.f32(float %x.fneg, float fsub (float -0.0, float bitcast (i32 ptrtoint…
[all …]
Dcos-intrinsic.ll36 %x.fneg = fsub float -0.0, %x
37 %cos = call float @llvm.cos.f32(float %x.fneg)
46 %x.fneg = fsub <2 x float> <float -0.0, float -0.0>, %x
47 %cos = call <2 x float> @llvm.cos.v2f32(<2 x float> %x.fneg)
67 %x.fabs.fneg = fsub float -0.0, %x.fabs
68 %cos = call float @llvm.cos.f32(float %x.fabs.fneg)
78 %x.fabs.fneg = fsub <2 x float> <float -0.0, float -0.0>, %x.fabs
79 %cos = call <2 x float> @llvm.cos.v2f32(<2 x float> %x.fabs.fneg)
/external/llvm/test/CodeGen/AMDGPU/
Dfneg.f64.ll7 %fneg = fsub double -0.000000e+00, %in
8 store double %fneg, double addrspace(1)* %out
16 %fneg = fsub <2 x double> <double -0.000000e+00, double -0.000000e+00>, %in
17 store <2 x double> %fneg, <2 x double> addrspace(1)* %out
32 …%fneg = fsub <4 x double> <double -0.000000e+00, double -0.000000e+00, double -0.000000e+00, doubl…
33 store <4 x double> %fneg, <4 x double> addrspace(1)* %out
38 ; (fneg (f64 bitcast (i64 a))) => (f64 bitcast (xor (i64 a), 0x80000000))
Dfneg.ll10 %fneg = fsub float -0.000000e+00, %in
11 store float %fneg, float addrspace(1)* %out
22 %fneg = fsub <2 x float> <float -0.000000e+00, float -0.000000e+00>, %in
23 store <2 x float> %fneg, <2 x float> addrspace(1)* %out
38 …%fneg = fsub <4 x float> <float -0.000000e+00, float -0.000000e+00, float -0.000000e+00, float -0.…
39 store <4 x float> %fneg, <4 x float> addrspace(1)* %out
44 ; (fneg (f32 bitcast (i32 a))) => (f32 bitcast (xor (i32 a), 0x80000000))
Dcommute_modifiers.ll30 %x.fneg.fabs = fsub float -0.000000e+00, %x.fabs
31 %z = fmul float 4.0, %x.fneg.fabs
44 %x.fneg = fsub float -0.000000e+00, %x
45 %z = fmul float 4.0, %x.fneg
94 %y.fneg = fsub float -0.000000e+00, %y
95 %z = fmul float %x, %y.fneg
112 %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
113 %z = fmul float %x, %y.fabs.fneg
150 %y.fabs.fneg = fsub float -0.000000e+00, %y.fabs
151 %z = fmul float %x.fabs, %y.fabs.fneg
Dllvm.AMDGPU.clamp.ll39 %src.fneg = fsub float -0.0, %src
40 …%clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg, float 0.0, float 1.0) nounwind readnone
52 %src.fneg.fabs = fsub float -0.0, %src.fabs
53 …%clamp = call float @llvm.AMDGPU.clamp.f32(float %src.fneg.fabs, float 0.0, float 1.0) nounwind re…
Dllvm.amdgcn.frexp.mant.ll30 %fneg.fabs.src = fsub float -0.0, %fabs.src
31 %frexp.mant = call float @llvm.amdgcn.frexp.mant.f32(float %fneg.fabs.src)
57 %fneg.fabs.src = fsub double -0.0, %fabs.src
58 %frexp.mant = call double @llvm.amdgcn.frexp.mant.f64(double %fneg.fabs.src)
Dllvm.amdgcn.frexp.exp.ll30 %fneg.fabs.src = fsub float -0.0, %fabs.src
31 %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.f32(float %fneg.fabs.src)
57 %fneg.fabs.src = fsub double -0.0, %fabs.src
58 %frexp.exp = call i32 @llvm.amdgcn.frexp.exp.f64(double %fneg.fabs.src)
Dcvt_flr_i32_f32.ll52 %x.fneg = fsub float -0.000000e+00, %x
53 %floor = call float @llvm.floor.f32(float %x.fneg) #1
66 %x.fabs.fneg = fsub float -0.000000e+00, %x.fabs
67 %floor = call float @llvm.floor.f32(float %x.fabs.fneg) #1

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