1; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
2; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -check-prefix=GCN %s
3
4; GCN-LABEL: {{^}}test_fmed3:
5; GCN: v_med3_f32 v{{[0-9]+}}, s{{[0-9]+}}, v{{[0-9]+}}, v{{[0-9]+}}
6define amdgpu_kernel void @test_fmed3(float addrspace(1)* %out, float %src0, float %src1, float %src2) #1 {
7  %mad = call float @llvm.amdgcn.fmed3.f32(float %src0, float %src1, float %src2)
8  store float %mad, float addrspace(1)* %out
9  ret void
10}
11
12; GCN-LABEL: {{^}}test_fmed3_srcmods:
13; GCN: v_med3_f32 v{{[0-9]+}}, -s{{[0-9]+}}, |v{{[0-9]+}}|, -|v{{[0-9]+}}|
14define amdgpu_kernel void @test_fmed3_srcmods(float addrspace(1)* %out, float %src0, float %src1, float %src2) #1 {
15  %src0.fneg = fsub float -0.0, %src0
16  %src1.fabs = call float @llvm.fabs.f32(float %src1)
17  %src2.fabs = call float @llvm.fabs.f32(float %src2)
18  %src2.fneg.fabs = fsub float -0.0, %src2.fabs
19  %mad = call float @llvm.amdgcn.fmed3.f32(float %src0.fneg, float %src1.fabs, float %src2.fneg.fabs)
20  store float %mad, float addrspace(1)* %out
21  ret void
22}
23
24declare float @llvm.amdgcn.fmed3.f32(float, float, float) #0
25declare float @llvm.fabs.f32(float) #0
26
27attributes #0 = { nounwind readnone }
28attributes #1 = { nounwind }
29