| /external/llvm/lib/Target/AVR/ |
| D | AVRTargetMachine.cpp | 29 static StringRef getCPU(StringRef CPU) { in getCPU() function
48 getCPU(CPU), FS, Options, getEffectiveRelocModel(RM), CM, OL), in AVRTargetMachine()
49 SubTarget(TT, getCPU(CPU), FS, *this) { in AVRTargetMachine()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
| D | AVRTargetMachine.cpp | 31 static StringRef getCPU(StringRef CPU) { in getCPU() function
55 : LLVMTargetMachine(T, AVRDataLayout, TT, getCPU(CPU), FS, Options, in AVRTargetMachine()
58 SubTarget(TT, getCPU(CPU), FS, *this) { in AVRTargetMachine()
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| /external/llvm/lib/MC/MCDisassembler/ |
| D | Disassembler.cpp | 159 if (DC->getCPU().empty()) in getItineraryLatency()
164 InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU()); in getItineraryLatency()
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| D | Disassembler.h | 121 StringRef getCPU() const { return CPU; } in getCPU() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/MC/MCDisassembler/ |
| D | Disassembler.cpp | 169 if (DC->getCPU().empty()) in getItineraryLatency()
174 InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU()); in getItineraryLatency()
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| D | Disassembler.h | 121 StringRef getCPU() const { return CPU; } in getCPU() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/MCTargetDesc/ |
| D | ARMTargetStreamer.cpp | 121 if (STI.getCPU() == "xscale") in getArchForCPU()
164 const StringRef CPUString = STI.getCPU(); in emitTargetAttributes()
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| /external/llvm/include/llvm/MC/ |
| D | MCSubtargetInfo.h | 66 StringRef getCPU() const { in getCPU() function
|
| /external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/MC/ |
| D | MCSubtargetInfo.h | 69 StringRef getCPU() const { return CPU; } in getCPU() function
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCDuplexInfo.cpp | 637 if (STI.getCPU().equals_lower("hexagonv4") || in isOrderedDuplexPair()
638 STI.getCPU().equals_lower("hexagonv5") || in isOrderedDuplexPair()
639 STI.getCPU().equals_lower("hexagonv55") || in isOrderedDuplexPair()
640 STI.getCPU().equals_lower("hexagonv60")) { in isOrderedDuplexPair()
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| D | HexagonMCTargetDesc.cpp | 413 auto F = ElfFlags.find(STI.getCPU()); in GetELFFlags()
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| D | HexagonAsmBackend.cpp | 776 StringRef CPUString = Hexagon_MC::selectHexagonCPU(STI.getCPU()); in createHexagonAsmBackend()
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| D | HexagonShuffler.cpp | 203 HexagonCVIResource::SetupTUL(&TUL, STI.getCPU()); in HexagonShuffler()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64SIMDInstrOpt.cpp | 223 std::string Subtarget = SchedModel.getSubtargetInfo()->getCPU(); in shouldReplaceInst()
292 std::string Subtarget = SchedModel.getSubtargetInfo()->getCPU(); in shouldExitEarly()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/ |
| D | MipsAsmBackend.cpp | 584 return new MipsAsmBackend(T, MRI, STI.getTargetTriple(), STI.getCPU(), in createMipsAsmBackend()
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonShuffler.cpp | 148 HexagonCVIResource::SetupTUL(&TUL, STI.getCPU()); in HexagonShuffler()
|
| /external/swiftshader/third_party/llvm-7.0/llvm/bindings/ocaml/target/ |
| D | llvm_target.mli | 194 [llvm::TargetMachine::getCPU]. *)
|
| /external/llvm/bindings/ocaml/target/ |
| D | llvm_target.mli | 194 [llvm::TargetMachine::getCPU]. *)
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| D | AMDGPUTargetStreamer.cpp | 345 EFlags |= getMACH(STI.getCPU()); in AMDGPUTargetELFStreamer()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/MCTargetDesc/ |
| D | X86MCTargetDesc.cpp | 318 if (STI.getCPU() == "btver2") { in isDependencyBreaking()
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| /external/clang/lib/Basic/ |
| D | Targets.cpp | 7259 const std::string& getCPU() const { return CPU; } in getCPU() function in __anond4862fe70111::MipsTargetInfo
7265 CPU = getCPU(); in initFeatureMap()
7298 const std::string ISARev = llvm::StringSwitch<std::string>(getCPU()) in getTargetDefines()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 485 sti.getCPU(), Options)) { in MipsAsmParser()
519 if (getSTI().getCPU() == "mips64r6" && inMicroMipsMode()) in MipsAsmParser()
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| /external/llvm/lib/Target/Mips/AsmParser/ |
| D | MipsAsmParser.cpp | 407 sti.getCPU(), Options)) { in MipsAsmParser()
|