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Searched refs:getDefRegState (Results 1 – 25 of 47) sorted by relevance

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/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DThumb2RegisterInfo.cpp49 .addReg(DestReg, getDefRegState(true), SubIdx) in emitLoadConstPool()
DARMLoadStoreOptimizer.cpp359 MIB = MIB.addReg(Regs[i].first, getDefRegState(isDef) in MergeOps()
748 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLSMultiple()
903 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLoadStore()
906 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : in MergeBaseUpdateLoadStore()
1056 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR()
1110 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1111 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
DMLxExpansionPass.cpp233 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
DARMBaseInstrInfo.h306 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
DThumb1FrameLowering.cpp355 MIB.addReg(Reg, getDefRegState(true)); in restoreCalleeSavedRegisters()
/external/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp81 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
85 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/MSP430/
DMSP430InstrInfo.cpp81 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
85 .addReg(DestReg, getDefRegState(true)).addFrameIndex(FrameIdx) in loadRegFromStackSlot()
/external/llvm/lib/Target/ARM/
DThumb1InstrInfo.cpp66 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
DARMLoadStoreOptimizer.cpp768 MIB.addReg(Base, getDefRegState(true)) in CreateLoadStoreMulti()
785 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
1263 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLSMultiple()
1387 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLoadStore()
1390 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : in MergeBaseUpdateLoadStore()
1560 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR()
1623 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1624 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
DThumbRegisterInfo.cpp77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
DMLxExpansionPass.cpp301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
DARMBaseInstrInfo.h411 return MIB.addReg(ARM::CPSR, getDefRegState(true) | getDeadRegState(isDead));
/external/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h372 inline unsigned getDefRegState(bool B) { in getDefRegState() function
397 return getDefRegState(RegOp.isDef()) | in getRegState()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DARMLoadStoreOptimizer.cpp800 MIB.addReg(Base, getDefRegState(true)) in CreateLoadStoreMulti()
816 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti()
1297 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLSMultiple()
1421 .addReg(Base, getDefRegState(true)) // WB base register in MergeBaseUpdateLoadStore()
1424 .addReg(MO.getReg(), (isLd ? getDefRegState(true) : in MergeBaseUpdateLoadStore()
1600 .addReg(Reg, getDefRegState(true) | getDeadRegState(RegDeadKill)) in InsertLDR_STR()
1665 .addReg(EvenReg, getDefRegState(isLd) | getDeadRegState(EvenDeadKill)) in FixInvalidRegPairOp()
1666 .addReg(OddReg, getDefRegState(isLd) | getDeadRegState(OddDeadKill)); in FixInvalidRegPairOp()
DThumb1InstrInfo.cpp74 .addReg(DestReg, getDefRegState(true)); in copyPhysReg()
DThumbRegisterInfo.cpp77 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb1LoadConstPool()
96 .addReg(DestReg, getDefRegState(true), SubIdx) in emitThumb2LoadConstPool()
DMLxExpansionPass.cpp301 .addReg(DstReg, getDefRegState(true) | getDeadRegState(DstDead)); in ExpandFPMLxInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DMachineInstrBuilder.h453 inline unsigned getDefRegState(bool B) { in getDefRegState() function
481 return getDefRegState(RegOp.isDef()) | in getRegState()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DMachineInstrBuilder.h246 inline unsigned getDefRegState(bool B) { in getDefRegState() function
/external/llvm/lib/CodeGen/
DMachineInstrBundle.cpp204 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineInstrBundle.cpp206 MIB.addReg(Reg, getDefRegState(true) | getDeadRegState(isDead) | in finalizeBundle()
/external/llvm/lib/Target/Lanai/
DLanaiMemAluCombiner.cpp260 InstrBuilder.addReg(Dest.getReg(), getDefRegState(true)); in insertMergedInstruction()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/
DLanaiMemAluCombiner.cpp260 InstrBuilder.addReg(Dest.getReg(), getDefRegState(true)); in insertMergedInstruction()
/external/llvm/lib/Target/AMDGPU/
DSIRegisterInfo.cpp469 unsigned SrcDstRegState = getDefRegState(!IsStore); in buildScratchLoadStore()
477 .addReg(SubReg, getDefRegState(!IsStore)) in buildScratchLoadStore()
/external/llvm/lib/Target/AArch64/
DAArch64FrameLowering.cpp1063 MIB.addReg(Reg2, getDefRegState(true)); in restoreCalleeSavedRegisters()
1068 MIB.addReg(Reg1, getDefRegState(true)) in restoreCalleeSavedRegisters()

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