/external/swiftshader/third_party/LLVM/lib/Target/Blackfin/ |
D | BlackfinInstrInfo.cpp | 106 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 112 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg() 120 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 126 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 134 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(0); in copyPhysReg() 139 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 147 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 153 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 181 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot() 189 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/ |
D | AVRExpandPseudoInsts.cpp | 155 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandArith() 156 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandArith() 160 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandArith() 161 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandArith() 188 .addReg(DstLoReg, getKillRegState(DstIsKill)) in expandLogic() 189 .addReg(SrcLoReg, getKillRegState(SrcIsKill)); in expandLogic() 196 .addReg(DstHiReg, getKillRegState(DstIsKill)) in expandLogic() 197 .addReg(SrcHiReg, getKillRegState(SrcIsKill)); in expandLogic() 236 .addReg(DstLoReg, getKillRegState(SrcIsKill)) in expandLogicImm() 246 .addReg(DstHiReg, getKillRegState(SrcIsKill)) in expandLogicImm() [all …]
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/external/llvm/lib/Target/Sparc/ |
D | SparcInstrInfo.cpp | 320 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 328 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 332 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 343 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 360 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 364 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 408 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot() 411 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot() 414 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot() 417 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/ |
D | SparcInstrInfo.cpp | 324 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 332 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 336 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 347 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 364 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 368 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 412 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot() 415 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot() 418 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot() 421 .addReg(SrcReg, getKillRegState(isKill)).addMemOperand(MMO); in storeRegToStackSlot() [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/ |
D | PPCInstrInfo.cpp | 143 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstruction() 144 .addReg(Reg1, getKillRegState(Reg1IsKill)) in commuteInstruction() 325 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 327 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 341 getKillRegState(isKill)), in StoreRegToStackSlot() 350 getKillRegState(isKill)), in StoreRegToStackSlot() 357 getKillRegState(isKill)), in StoreRegToStackSlot() 366 getKillRegState(isKill)), in StoreRegToStackSlot() 372 getKillRegState(isKill)), in StoreRegToStackSlot() 377 getKillRegState(isKill)), in StoreRegToStackSlot() [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/SystemZ/ |
D | SystemZInstrBuilder.h | 77 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset() 85 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(0) in addRegReg() 86 .addReg(Reg2, getKillRegState(isKill2)); in addRegReg()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
D | Thumb1InstrInfo.cpp | 53 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg() 63 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg() 71 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 99 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
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D | MLxExpansionPass.cpp | 294 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction() 295 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction() 305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction() 306 .addReg(AccReg, getKillRegState(AccKill)); in ExpandFPMLxInstruction() 308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
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D | ARMLoadStoreOptimizer.cpp | 735 .addReg(Base, getKillRegState(KillOldBase)); in CreateLoadStoreMulti() 738 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti() 748 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti() 754 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti() 759 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti() 801 .addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti() 810 MIB.addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti() 816 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti() 837 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second)) in CreateLoadStoreDouble() 838 .addReg(Regs[1].first, getKillRegState(Regs[1].second)); in CreateLoadStoreDouble() [all …]
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/external/swiftshader/third_party/LLVM/lib/Target/Sparc/ |
D | SparcInstrInfo.cpp | 275 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 278 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 281 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 297 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot() 300 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot() 303 .addReg(SrcReg, getKillRegState(isKill)); in storeRegToStackSlot()
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/external/swiftshader/third_party/LLVM/lib/Target/ARM/ |
D | MLxExpansionPass.cpp | 226 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction() 227 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction() 237 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction() 238 .addReg(AccReg, getKillRegState(AccKill)); in ExpandFPMLxInstruction() 240 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
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D | Thumb1InstrInfo.cpp | 40 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg() 69 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
D | AlphaInstrInfo.cpp | 128 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 132 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 136 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 157 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot() 161 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot() 165 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
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/external/swiftshader/third_party/LLVM/lib/Target/X86/ |
D | X86InstrBuilder.h | 110 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset() 118 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg() 119 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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/external/llvm/lib/Target/ARM/ |
D | Thumb1InstrInfo.cpp | 54 .addReg(SrcReg, getKillRegState(KillSrc))); in copyPhysReg() 64 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 91 .addReg(SrcReg, getKillRegState(isKill)) in storeRegToStackSlot()
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D | MLxExpansionPass.cpp | 294 .addReg(Src1Reg, getKillRegState(Src1Kill)) in ExpandFPMLxInstruction() 295 .addReg(Src2Reg, getKillRegState(Src2Kill)); in ExpandFPMLxInstruction() 305 MIB.addReg(TmpReg, getKillRegState(true)) in ExpandFPMLxInstruction() 306 .addReg(AccReg, getKillRegState(AccKill)); in ExpandFPMLxInstruction() 308 MIB.addReg(AccReg).addReg(TmpReg, getKillRegState(true)); in ExpandFPMLxInstruction()
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D | ARMLoadStoreOptimizer.cpp | 707 .addReg(Base, getKillRegState(KillOldBase)); in CreateLoadStoreMulti() 710 .addReg(Base, getKillRegState(KillOldBase)) in CreateLoadStoreMulti() 720 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset/4) in CreateLoadStoreMulti() 725 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset) in CreateLoadStoreMulti() 729 .addReg(Base, getKillRegState(KillOldBase)).addImm(Offset) in CreateLoadStoreMulti() 769 .addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti() 779 MIB.addReg(Base, getKillRegState(BaseKill)); in CreateLoadStoreMulti() 785 MIB.addReg(R.first, getDefRegState(isDef) | getKillRegState(R.second)); in CreateLoadStoreMulti() 806 MIB.addReg(Regs[0].first, getKillRegState(Regs[0].second)) in CreateLoadStoreDouble() 807 .addReg(Regs[1].first, getKillRegState(Regs[1].second)); in CreateLoadStoreDouble() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/ |
D | BPFInstrInfo.cpp | 38 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 41 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 136 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot() 141 .addReg(SrcReg, getKillRegState(IsKill)) in storeRegToStackSlot()
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/external/llvm/lib/Target/PowerPC/ |
D | PPCInstrInfo.cpp | 382 .addReg(Reg2, getKillRegState(Reg2IsKill)) in commuteInstructionImpl() 383 .addReg(Reg1, getKillRegState(Reg1IsKill)) in commuteInstructionImpl() 890 getKillRegState(KillSrc); in copyPhysReg() 902 getKillRegState(KillSrc); in copyPhysReg() 907 getKillRegState(KillSrc); in copyPhysReg() 949 .addReg(SrcReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 951 BuildMI(MBB, I, DL, MCID, DestReg).addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 970 getKillRegState(isKill)), in StoreRegToStackSlot() 976 getKillRegState(isKill)), in StoreRegToStackSlot() 981 getKillRegState(isKill)), in StoreRegToStackSlot() [all …]
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/external/llvm/lib/Target/X86/ |
D | X86InstrBuilder.h | 138 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset() 146 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg() 147 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
D | X86InstrBuilder.h | 160 return addOffset(MIB.addReg(Reg, getKillRegState(isKill)), Offset); in addRegOffset() 168 return MIB.addReg(Reg1, getKillRegState(isKill1)).addImm(1) in addRegReg() 169 .addReg(Reg2, getKillRegState(isKill2)).addImm(0).addReg(0); in addRegReg()
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/external/llvm/lib/CodeGen/SelectionDAG/ |
D | FastISel.cpp | 1825 .addReg(Op0, getKillRegState(Op0IsKill)); in fastEmitInst_r() 1828 .addReg(Op0, getKillRegState(Op0IsKill)); in fastEmitInst_r() 1848 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr() 1849 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr() 1852 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr() 1853 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr() 1874 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr() 1875 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr() 1876 .addReg(Op2, getKillRegState(Op2IsKill)); in fastEmitInst_rrr() 1879 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr() [all …]
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/external/llvm/lib/Target/AArch64/ |
D | AArch64InstrInfo.cpp | 1892 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI); in copyPhysRegTuple() 1920 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg() 1923 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg() 1944 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); in copyPhysReg() 1949 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 1960 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg() 1970 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 2038 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() 2042 .addReg(SrcReg, getKillRegState(KillSrc)) in copyPhysReg() 2063 .addReg(SrcReg, getKillRegState(KillSrc)); in copyPhysReg() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
D | FastISel.cpp | 2018 .addReg(Op0, getKillRegState(Op0IsKill)); in fastEmitInst_r() 2021 .addReg(Op0, getKillRegState(Op0IsKill)); in fastEmitInst_r() 2041 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr() 2042 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr() 2045 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rr() 2046 .addReg(Op1, getKillRegState(Op1IsKill)); in fastEmitInst_rr() 2067 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr() 2068 .addReg(Op1, getKillRegState(Op1IsKill)) in fastEmitInst_rrr() 2069 .addReg(Op2, getKillRegState(Op2IsKill)); in fastEmitInst_rrr() 2072 .addReg(Op0, getKillRegState(Op0IsKill)) in fastEmitInst_rrr() [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/ |
D | XCoreRegisterInfo.cpp | 78 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPImmInst() 114 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertFPConstInst() 148 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPImmInst() 191 .addReg(Reg, getKillRegState(MI.getOperand(0).isKill())) in InsertSPConstInst()
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