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Searched refs:getMachineOpValue (Results 1 – 25 of 40) sorted by relevance

12

/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenMCCodeEmitter.inc3503 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3507 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3519 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3523 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3527 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3539 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3542 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
3545 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
3552 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
3562 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCCodeEmitter.cpp60 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
172 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in SystemZMCCodeEmitter
186 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDAddr12Encoding()
187 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDAddr12Encoding()
196 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDAddr20Encoding()
197 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDAddr20Encoding()
206 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDXAddr12Encoding()
207 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDXAddr12Encoding()
208 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); in getBDXAddr12Encoding()
217 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDXAddr20Encoding()
[all …]
/external/llvm/lib/Target/SystemZ/MCTargetDesc/
DSystemZMCCodeEmitter.cpp52 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
137 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in SystemZMCCodeEmitter
151 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDAddr12Encoding()
152 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDAddr12Encoding()
161 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDAddr20Encoding()
162 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDAddr20Encoding()
171 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDXAddr12Encoding()
172 uint64_t Disp = getMachineOpValue(MI, MI.getOperand(OpNum + 1), Fixups, STI); in getBDXAddr12Encoding()
173 uint64_t Index = getMachineOpValue(MI, MI.getOperand(OpNum + 2), Fixups, STI); in getBDXAddr12Encoding()
182 uint64_t Base = getMachineOpValue(MI, MI.getOperand(OpNum), Fixups, STI); in getBDXAddr20Encoding()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenMCCodeEmitter.inc2702 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2705 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
2738 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2741 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
2744 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2750 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
2753 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
2766 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2784 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
2795 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenMCCodeEmitter.inc4619 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4626 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4650 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4653 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4656 op = getMachineOpValue(MI, MI.getOperand(3), Fixups, STI);
4659 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4668 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
4671 op = getMachineOpValue(MI, MI.getOperand(1), Fixups, STI);
4674 op = getMachineOpValue(MI, MI.getOperand(2), Fixups, STI);
4681 op = getMachineOpValue(MI, MI.getOperand(0), Fixups, STI);
[all …]
/external/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp96 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
157 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
169 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
195 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
221 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; in getMemRIEncoding()
225 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; in getMemRIEncoding()
240 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; in getMemRIXEncoding()
244 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; in getMemRIXEncoding()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp102 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
164 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getDirectBrEncoding()
176 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getCondBrEncoding()
189 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsDirectBrEncoding()
202 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getAbsCondBrEncoding()
214 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups, STI); in getImm16Encoding()
228 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 16; in getMemRIEncoding()
232 return (getMachineOpValue(MI, MO, Fixups, STI) & 0xFFFF) | RegBits; in getMemRIEncoding()
246 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI) << 14; in getMemRIXEncoding()
250 return ((getMachineOpValue(MI, MO, Fixups, STI) >> 2) & 0x3FFF) | RegBits; in getMemRIXEncoding()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/MCTargetDesc/
DPPCMCCodeEmitter.cpp55 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO,
89 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getDirectBrEncoding()
100 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getCondBrEncoding()
111 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getHA16Encoding()
122 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO, Fixups); in getLO16Encoding()
135 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 16; in getMemRIEncoding()
139 return (getMachineOpValue(MI, MO, Fixups) & 0xFFFF) | RegBits; in getMemRIEncoding()
153 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups) << 14; in getMemRIXEncoding()
157 return (getMachineOpValue(MI, MO, Fixups) & 0x3FFF) | RegBits; in getMemRIXEncoding()
177 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in PPCMCCodeEmitter
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DARMCodeEmitter.cpp150 unsigned getMachineOpValue(const MachineInstr &MI,
152 unsigned getMachineOpValue(const MachineInstr &MI, unsigned OpIdx) const { in getMachineOpValue() function in __anon6d3f1ab80111::ARMCodeEmitter
153 return getMachineOpValue(MI, MI.getOperand(OpIdx)); in getMachineOpValue()
439 unsigned ARMCodeEmitter::getMachineOpValue(const MachineInstr &MI, in getMachineOpValue() function in ARMCodeEmitter
697 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; in emitMOVi32immInstruction()
712 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; in emitMOVi32immInstruction()
735 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; in emitMOVi2piecesInstruction()
750 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRdShift; in emitMOVi2piecesInstruction()
753 Binary |= getMachineOpValue(MI, MO0) << ARMII::RegRnShift; in emitMOVi2piecesInstruction()
777 Binary |= getMachineOpValue(MI, 0) << ARMII::RegRdShift; in emitLEApcrelJTInstruction()
[all …]
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp560 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); in getUImm5Lsl2Encoding()
760 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in MipsMCCodeEmitter
786 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; in getMemEncoding()
787 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncoding()
801 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), in getMemEncodingMMImm4()
803 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMImm4()
815 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), in getMemEncodingMMImm4Lsl1()
817 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMImm4Lsl1()
829 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), in getMemEncodingMMImm4Lsl2()
831 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMImm4Lsl2()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/PowerPC/
DPPCCodeEmitter.cpp60 unsigned getMachineOpValue(const MachineInstr &MI,
182 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getDirectBrEncoding()
198 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getHA16Encoding()
207 if (MO.isReg() || MO.isImm()) return getMachineOpValue(MI, MO); in getLO16Encoding()
218 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 16; in getMemRIEncoding()
222 return (getMachineOpValue(MI, MO) & 0xFFFF) | RegBits; in getMemRIEncoding()
234 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo+1)) << 14; in getMemRIXEncoding()
238 return (getMachineOpValue(MI, MO) & 0x3FFF) | RegBits; in getMemRIXEncoding()
245 unsigned PPCCodeEmitter::getMachineOpValue(const MachineInstr &MI, in getMachineOpValue() function in PPCCodeEmitter
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp532 unsigned Res = getMachineOpValue(MI, MO, Fixups, STI); in getUImm5Lsl2Encoding()
734 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in MipsMCCodeEmitter
760 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo),Fixups, STI) << 16; in getMemEncoding()
761 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), Fixups, STI); in getMemEncoding()
775 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), in getMemEncodingMMImm4()
777 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMImm4()
789 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), in getMemEncodingMMImm4Lsl1()
791 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMImm4Lsl1()
803 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo), in getMemEncodingMMImm4Lsl2()
805 unsigned OffBits = getMachineOpValue(MI, MI.getOperand(OpNo+1), in getMemEncodingMMImm4Lsl2()
[all …]
/external/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcMCCodeEmitter.cpp57 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
106 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI); in encodeInstruction()
116 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in SparcMCCodeEmitter
148 return getMachineOpValue(MI, MO, Fixups, STI); in getCallTargetOpValue()
183 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchTargetOpValue()
196 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchPredTargetOpValue()
208 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchOnRegTargetOpValue()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Sparc/MCTargetDesc/
DSparcMCCodeEmitter.cpp69 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
115 uint64_t op = getMachineOpValue(MI, MO, Fixups, STI); in encodeInstruction()
124 getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function in SparcMCCodeEmitter
155 return getMachineOpValue(MI, MO, Fixups, STI); in getCallTargetOpValue()
190 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchTargetOpValue()
203 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchPredTargetOpValue()
216 return getMachineOpValue(MI, MO, Fixups, STI); in getBranchOnRegTargetOpValue()
/external/swiftshader/third_party/LLVM/lib/Target/Mips/
DMipsCodeEmitter.cpp102 unsigned getMachineOpValue(const MachineInstr &MI,
163 unsigned RegBits = getMachineOpValue(MI, MI.getOperand(OpNo)) << 16; in getMemEncoding()
165 (getMachineOpValue(MI, MI.getOperand(OpNo+1)) & 0xFFFF) | RegBits; in getMemEncoding()
171 return getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; in getSizeExtEncoding()
177 return getMachineOpValue(MI, MI.getOperand(OpNo-1)) + in getSizeInsEncoding()
178 getMachineOpValue(MI, MI.getOperand(OpNo)) - 1; in getSizeInsEncoding()
183 unsigned MipsCodeEmitter::getMachineOpValue(const MachineInstr &MI, in getMachineOpValue() function in MipsCodeEmitter
/external/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiMCCodeEmitter.cpp58 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
112 unsigned LanaiMCCodeEmitter::getMachineOpValue( in getMachineOpValue() function in llvm::__anonccb3e86b0111::LanaiMCCodeEmitter
215 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo); in getRiMemoryOpValue()
286 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo); in getSplsOpValue()
296 return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo); in getCallTargetOpValue()
309 return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo); in getBranchTargetOpValue()
/external/swiftshader/third_party/LLVM/lib/Target/MBlaze/MCTargetDesc/
DMBlazeMCCodeEmitter.cpp50 unsigned getMachineOpValue(const MCInst &MI,const MCOperand &MO) const;
51 unsigned getMachineOpValue(const MCInst &MI, unsigned OpIdx) const { in getMachineOpValue() function in __anon2b1e74e30111::MBlazeMCCodeEmitter
52 return getMachineOpValue(MI, MI.getOperand(OpIdx)); in getMachineOpValue()
108 unsigned MBlazeMCCodeEmitter::getMachineOpValue(const MCInst &MI, in getMachineOpValue() function in MBlazeMCCodeEmitter
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Lanai/MCTargetDesc/
DLanaiMCCodeEmitter.cpp58 unsigned getMachineOpValue(const MCInst &Inst, const MCOperand &MCOp,
110 unsigned LanaiMCCodeEmitter::getMachineOpValue( in getMachineOpValue() function in llvm::LanaiMCCodeEmitter
213 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo); in getRiMemoryOpValue()
284 getMachineOpValue(Inst, Op2, Fixups, SubtargetInfo); in getSplsOpValue()
294 return getMachineOpValue(Inst, MCOp, Fixups, SubtargetInfo); in getBranchTargetOpValue()
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp59 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
254 return getMachineOpValue(MI, MO, Fixups, STI); in getSOPPBrEncoding()
257 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, in getMachineOpValue() function in SIMCCodeEmitter
DR600MCCodeEmitter.cpp50 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
155 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, in getMachineOpValue() function in R600MCCodeEmitter
DAMDGPUMCCodeEmitter.h35 virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO, in getMachineOpValue() function
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/BPF/MCTargetDesc/
DBPFMCCodeEmitter.cpp54 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
86 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI, in getMachineOpValue() function in BPFMCCodeEmitter
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/MCTargetDesc/
DSIMCCodeEmitter.cpp63 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
325 return getMachineOpValue(MI, MO, Fixups, STI); in getSOPPBrEncoding()
396 uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI, in getMachineOpValue() function in SIMCCodeEmitter
DR600MCCodeEmitter.cpp54 uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
171 uint64_t R600MCCodeEmitter::getMachineOpValue(const MCInst &MI, in getMachineOpValue() function in R600MCCodeEmitter
/external/llvm/lib/Target/BPF/MCTargetDesc/
DBPFMCCodeEmitter.cpp50 unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
76 unsigned BPFMCCodeEmitter::getMachineOpValue(const MCInst &MI, in getMachineOpValue() function in BPFMCCodeEmitter

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