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Searched refs:getOperand (Results 1 – 25 of 1857) sorted by relevance

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/external/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/X86/InstPrinter/
DX86InstComments.cpp37 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
38 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
39 DecodeINSERTPSMask(MI->getOperand(3).getImm(), ShuffleMask); in EmitAnyX86InstComments()
43 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
44 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
49 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
50 Src1Name = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
55 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
58 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
59 DecodePSHUFMask(4, MI->getOperand(MI->getNumOperands()-1).getImm(), in EmitAnyX86InstComments()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp218 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
241 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
271 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
276 AccName = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
277 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
282 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
287 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
288 Mul2Name = getRegName(MI->getOperand(1).getReg()); in printFMA3Comments()
293 Mul2Name = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMA3Comments()
298 Mul1Name = getRegName(MI->getOperand(NumOperands-(RegForm?2:6)).getReg()); in printFMA3Comments()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/
DAArch64GenAsmWriter1.inc13572 MI->getOperand(0).getReg() == AArch64::WZR &&
13573 MI->getOperand(1).isReg() &&
13574 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) {
13582 MI->getOperand(0).getReg() == AArch64::WZR &&
13583 MI->getOperand(1).isReg() &&
13584 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
13585 MI->getOperand(2).isReg() &&
13586 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
13587 MI->getOperand(3).isImm() &&
13588 MI->getOperand(3).getImm() == 0) {
[all …]
DAArch64GenAsmWriter.inc12884 MI->getOperand(0).getReg() == AArch64::WZR &&
12885 MI->getOperand(1).isReg() &&
12886 MRI.getRegClass(AArch64::GPR32spRegClassID).contains(MI->getOperand(1).getReg())) {
12894 MI->getOperand(0).getReg() == AArch64::WZR &&
12895 MI->getOperand(1).isReg() &&
12896 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(1).getReg()) &&
12897 MI->getOperand(2).isReg() &&
12898 MRI.getRegClass(AArch64::GPR32RegClassID).contains(MI->getOperand(2).getReg()) &&
12899 MI->getOperand(3).isImm() &&
12900 MI->getOperand(3).getImm() == 0) {
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/SystemZ/
DSystemZAsmPrinter.cpp34 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
35 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
38 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
39 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
40 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
48 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
49 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
52 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
53 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
54 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
[all …]
/external/llvm/lib/Target/X86/InstPrinter/
DX86InstComments.cpp176 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandVectorVT()
281 MaskRegName = getRegName(MI->getOperand(1).getReg()); in getMaskName()
345 MaskRegName = getRegName(MI->getOperand(2).getReg()); in getMaskName()
384 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
389 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
391 MI->getOperand(NumOperands - 1).getImm(), in EmitAnyX86InstComments()
393 Src1Name = getRegName(MI->getOperand(1).getReg()); in EmitAnyX86InstComments()
394 DestName = getRegName(MI->getOperand(0).getReg()); in EmitAnyX86InstComments()
400 Src2Name = getRegName(MI->getOperand(2).getReg()); in EmitAnyX86InstComments()
405 if (MI->getOperand(NumOperands - 1).isImm()) in EmitAnyX86InstComments()
[all …]
/external/swiftshader/third_party/LLVM/lib/Transforms/InstCombine/
DInstCombineVectorOps.cpp26 Constant *Op0 = C->getOperand(0); in CheapToScalarize()
28 if (C->getOperand(i) != Op0) in CheapToScalarize()
38 isa<ConstantInt>(I->getOperand(2))) in CheapToScalarize()
44 (CheapToScalarize(BO->getOperand(0), isConstant) || in CheapToScalarize()
45 CheapToScalarize(BO->getOperand(1), isConstant))) in CheapToScalarize()
49 (CheapToScalarize(CI->getOperand(0), isConstant) || in CheapToScalarize()
50 CheapToScalarize(CI->getOperand(1), isConstant))) in CheapToScalarize()
60 if (isa<ConstantAggregateZero>(SVI->getOperand(2))) in getShuffleMask()
62 if (isa<UndefValue>(SVI->getOperand(2))) in getShuffleMask()
66 const ConstantVector *CP = cast<ConstantVector>(SVI->getOperand(2)); in getShuffleMask()
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/ARM/
DARMGenMCPseudoLowering.inc19 lowerOperand(MI->getOperand(0), MCOp);
32 lowerOperand(MI->getOperand(0), MCOp);
35 lowerOperand(MI->getOperand(1), MCOp);
38 lowerOperand(MI->getOperand(2), MCOp);
40 lowerOperand(MI->getOperand(3), MCOp);
43 lowerOperand(MI->getOperand(4), MCOp);
47 if (lowerOperand(MI->getOperand(i), MCOp))
57 lowerOperand(MI->getOperand(0), MCOp);
60 lowerOperand(MI->getOperand(1), MCOp);
63 lowerOperand(MI->getOperand(2), MCOp);
[all …]
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/Mips/
DMipsGenMCPseudoLowering.inc19 lowerOperand(MI->getOperand(0), MCOp);
22 lowerOperand(MI->getOperand(1), MCOp);
25 lowerOperand(MI->getOperand(2), MCOp);
35 lowerOperand(MI->getOperand(0), MCOp);
38 lowerOperand(MI->getOperand(1), MCOp);
41 lowerOperand(MI->getOperand(2), MCOp);
51 lowerOperand(MI->getOperand(0), MCOp);
54 lowerOperand(MI->getOperand(1), MCOp);
57 lowerOperand(MI->getOperand(2), MCOp);
71 lowerOperand(MI->getOperand(0), MCOp);
[all …]
/external/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp111 LIS->getInterval(MI->getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
129 unsigned AddendSrcReg = AddendMI->getOperand(1).getReg(); in processBlock()
131 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
137 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
163 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) { in processBlock()
185 unsigned OldFMAReg = MI->getOperand(0).getReg(); in processBlock()
189 unsigned Reg2 = MI->getOperand(2).getReg(); in processBlock()
190 unsigned Reg3 = MI->getOperand(3).getReg(); in processBlock()
217 unsigned KilledProdReg = MI->getOperand(KilledProdOp).getReg(); in processBlock()
218 unsigned OtherProdReg = MI->getOperand(OtherProdOp).getReg(); in processBlock()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/XCore/
DXCoreISelDAGToDAG.cpp100 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
101 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
115 Base = Addr.getOperand(0); in SelectADDRdpii()
121 if ((Addr.getOperand(0).getOpcode() == XCoreISD::DPRelativeWrapper) in SelectADDRdpii()
122 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRdpii()
125 Base = Addr.getOperand(0).getOperand(0); in SelectADDRdpii()
136 Base = Addr.getOperand(0); in SelectADDRcpii()
142 if ((Addr.getOperand(0).getOpcode() == XCoreISD::CPRelativeWrapper) in SelectADDRcpii()
143 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRcpii()
146 Base = Addr.getOperand(0).getOperand(0); in SelectADDRcpii()
[all …]
/external/swiftshader/third_party/LLVM/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp60 const MCOperand &Dst = MI->getOperand(0); in printInst()
61 const MCOperand &MO1 = MI->getOperand(1); in printInst()
62 const MCOperand &MO2 = MI->getOperand(2); in printInst()
63 const MCOperand &MO3 = MI->getOperand(3); in printInst()
80 const MCOperand &Dst = MI->getOperand(0); in printInst()
81 const MCOperand &MO1 = MI->getOperand(1); in printInst()
82 const MCOperand &MO2 = MI->getOperand(2); in printInst()
104 MI->getOperand(0).getReg() == ARM::SP) { in printInst()
114 if (Opcode == ARM::STR_PRE_IMM && MI->getOperand(2).getReg() == ARM::SP && in printInst()
115 MI->getOperand(3).getImm() == -4) { in printInst()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/PowerPC/
DPPCVSXFMAMutate.cpp112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
130 unsigned AddendSrcReg = AddendMI->getOperand(1).getReg(); in processBlock()
132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
164 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) { in processBlock()
186 unsigned OldFMAReg = MI.getOperand(0).getReg(); in processBlock()
190 unsigned Reg2 = MI.getOperand(2).getReg(); in processBlock()
191 unsigned Reg3 = MI.getOperand(3).getReg(); in processBlock()
218 unsigned KilledProdReg = MI.getOperand(KilledProdOp).getReg(); in processBlock()
219 unsigned OtherProdReg = MI.getOperand(OtherProdOp).getReg(); in processBlock()
[all …]
DPPCMIPeephole.cpp146 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
149 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) in getKnownLeadingZeroCount()
150 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
155 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) in getKnownLeadingZeroCount()
156 return 32 + MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
159 uint16_t Imm = MI->getOperand(2).getImm(); in getKnownLeadingZeroCount()
289 int Immed = MI.getOperand(3).getImm(); in simplifyCode()
300 TRI->lookThruCopyLike(MI.getOperand(1).getReg(), MRI); in simplifyCode()
302 TRI->lookThruCopyLike(MI.getOperand(2).getReg(), MRI); in simplifyCode()
317 TRI->lookThruCopyLike(DefMI->getOperand(1).getReg(), MRI); in simplifyCode()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/
DRISCVMergeBaseOffset.cpp84 HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI || in detectLuiAddiGlobal()
85 HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress || in detectLuiAddiGlobal()
86 HiLUI.getOperand(1).getOffset() != 0 || in detectLuiAddiGlobal()
87 !MRI->hasOneUse(HiLUI.getOperand(0).getReg())) in detectLuiAddiGlobal()
89 unsigned HiLuiDestReg = HiLUI.getOperand(0).getReg(); in detectLuiAddiGlobal()
92 LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO || in detectLuiAddiGlobal()
93 LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress || in detectLuiAddiGlobal()
94 LoADDI->getOperand(2).getOffset() != 0 || in detectLuiAddiGlobal()
95 !MRI->hasOneUse(LoADDI->getOperand(0).getReg())) in detectLuiAddiGlobal()
107 HiLUI.getOperand(1).setOffset(Offset); in foldOffset()
[all …]
/external/llvm/lib/Target/AMDGPU/
DR600ClauseMergePass.cpp77 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::COUNT)) in getCFAluSize()
84 .getOperand(TII->getOperandIdx(MI.getOpcode(), AMDGPU::OpName::Enabled)) in isCFAluEnabled()
101 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
126 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
127 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
128 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
129 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
130 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
131 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
142 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600ClauseMergePass.cpp88 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
95 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
112 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
137 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
138 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
139 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
140 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
141 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
142 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
153 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
[all …]
/external/llvm/lib/Target/NVPTX/
DNVPTXISelDAGToDAG.cpp525 unsigned IID = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue(); in tryIntrinsicChain()
593 unsigned IID = cast<ConstantSDNode>(N->getOperand(0))->getZExtValue(); in tryIntrinsicNoChain()
605 SDValue Wrapper = N->getOperand(1); in SelectTexSurfHandle()
606 SDValue GlobalVal = Wrapper.getOperand(0); in SelectTexSurfHandle()
612 SDValue Src = N->getOperand(0); in SelectAddrSpaceCast()
734 SDValue Chain = N->getOperand(0); in tryLoad()
735 SDValue N1 = N->getOperand(1); in tryLoad()
916 SDValue Chain = N->getOperand(0); in tryLoadVector()
917 SDValue Op1 = N->getOperand(1); in tryLoadVector()
958 N->getOperand(N->getNumOperands() - 1))->getZExtValue(); in tryLoadVector()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp88 const MCOperand &Dst = MI->getOperand(0); in printInst()
89 const MCOperand &MO1 = MI->getOperand(1); in printInst()
90 const MCOperand &MO2 = MI->getOperand(2); in printInst()
91 const MCOperand &MO3 = MI->getOperand(3); in printInst()
111 const MCOperand &Dst = MI->getOperand(0); in printInst()
112 const MCOperand &MO1 = MI->getOperand(1); in printInst()
113 const MCOperand &MO2 = MI->getOperand(2); in printInst()
138 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
152 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
153 MI->getOperand(3).getImm() == -4) { in printInst()
[all …]
/external/llvm/lib/Target/ARM/InstPrinter/
DARMInstPrinter.cpp80 const MCOperand &Dst = MI->getOperand(0); in printInst()
81 const MCOperand &MO1 = MI->getOperand(1); in printInst()
82 const MCOperand &MO2 = MI->getOperand(2); in printInst()
83 const MCOperand &MO3 = MI->getOperand(3); in printInst()
103 const MCOperand &Dst = MI->getOperand(0); in printInst()
104 const MCOperand &MO1 = MI->getOperand(1); in printInst()
105 const MCOperand &MO2 = MI->getOperand(2); in printInst()
130 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
144 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
145 MI->getOperand(3).getImm() == -4) { in printInst()
[all …]
/external/llvm/lib/Target/Mips/MCTargetDesc/
DMipsMCCodeEmitter.cpp55 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
57 int64_t Shift = Inst.getOperand(2).getImm(); in LowerLargeShift()
63 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
101 assert(InstIn.getOperand(2).isImm()); in LowerDins()
102 int64_t pos = InstIn.getOperand(2).getImm(); in LowerDins()
103 assert(InstIn.getOperand(3).isImm()); in LowerDins()
104 int64_t size = InstIn.getOperand(3).getImm(); in LowerDins()
110 InstIn.getOperand(2).setImm(pos - 32); in LowerDins()
116 InstIn.getOperand(3).setImm(size - 32); in LowerDins()
126 unsigned RegOp0 = Inst.getOperand(0).getReg(); in LowerCompactBranch()
[all …]
/external/llvm/lib/Target/Hexagon/MCTargetDesc/
DHexagonMCCompound.cpp100 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
101 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
102 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
114 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
115 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
126 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
127 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
136 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
145 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
146 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/
DAVRExpandPseudoInsts.cpp144 unsigned DstReg = MI.getOperand(0).getReg(); in expandArith()
145 unsigned SrcReg = MI.getOperand(2).getReg(); in expandArith()
146 bool DstIsDead = MI.getOperand(0).isDead(); in expandArith()
147 bool DstIsKill = MI.getOperand(1).isKill(); in expandArith()
148 bool SrcIsKill = MI.getOperand(2).isKill(); in expandArith()
149 bool ImpIsDead = MI.getOperand(3).isDead(); in expandArith()
164 MIBHI->getOperand(3).setIsDead(); in expandArith()
167 MIBHI->getOperand(4).setIsKill(); in expandArith()
177 unsigned DstReg = MI.getOperand(0).getReg(); in expandLogic()
178 unsigned SrcReg = MI.getOperand(2).getReg(); in expandLogic()
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/XCore/
DXCoreISelDAGToDAG.cpp97 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
98 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
128 OutOps.push_back(Op.getOperand(0)); in SelectInlineAsmMemoryOperand()
164 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
165 N->getOperand(2) }; in Select()
171 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
172 N->getOperand(2) }; in Select()
178 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
179 N->getOperand(2), N->getOperand(3) }; in Select()
185 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
[all …]

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