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Searched refs:hasVRegLiveness (Results 1 – 6 of 6) sorted by relevance

/external/llvm/include/llvm/CodeGen/
DMachineScheduler.h273 virtual bool hasVRegLiveness() const { return false; } in hasVRegLiveness() function
405 bool hasVRegLiveness() const override { return true; } in hasVRegLiveness() function
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DMachineScheduler.h309 virtual bool hasVRegLiveness() const { return false; } in hasVRegLiveness() function
446 bool hasVRegLiveness() const override { return true; } in hasVRegLiveness() function
/external/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp28 assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness"); in initialize()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AMDGPU/
DR600MachineScheduler.cpp29 assert(dag->hasVRegLiveness() && "R600SchedStrategy needs vreg liveness"); in initialize()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMachineScheduler.cpp1795 assert(DAG->hasVRegLiveness() && "Expect VRegs with LiveIntervals"); in apply()
2618 assert(dag->hasVRegLiveness() && in initialize()
3393 assert(dag->hasVRegLiveness() && "ILPScheduler needs vreg liveness"); in initialize()
3600 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ? in getNodeLabel()
3615 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ? in getNodeAttributes()
/external/llvm/lib/CodeGen/
DMachineScheduler.cpp1725 assert(DAG->hasVRegLiveness() && "Expect VRegs with LiveIntervals"); in apply()
2536 assert(dag->hasVRegLiveness() && in initialize()
3314 assert(dag->hasVRegLiveness() && "ILPScheduler needs vreg liveness"); in initialize()
3511 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ? in getNodeLabel()
3525 const SchedDFSResult *DFS = DAG->hasVRegLiveness() ? in getNodeAttributes()