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/external/vixl/src/aarch64/
Ddecoder-aarch64.cc35 void Decoder::DecodeInstruction(const Instruction* instr) { in DecodeInstruction() argument
36 if (instr->ExtractBits(28, 27) == 0) { in DecodeInstruction()
37 VisitUnallocated(instr); in DecodeInstruction()
39 switch (instr->ExtractBits(27, 24)) { in DecodeInstruction()
42 DecodePCRelAddressing(instr); in DecodeInstruction()
47 DecodeAddSubImmediate(instr); in DecodeInstruction()
62 DecodeDataProcessing(instr); in DecodeInstruction()
68 DecodeLogical(instr); in DecodeInstruction()
74 DecodeBitfieldExtract(instr); in DecodeInstruction()
89 DecodeBranchSystemException(instr); in DecodeInstruction()
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Dinstrument-aarch64.cc257 void Instrument::VisitPCRelAddressing(const Instruction* instr) { in VisitPCRelAddressing() argument
258 USE(instr); in VisitPCRelAddressing()
265 void Instrument::VisitAddSubImmediate(const Instruction* instr) { in VisitAddSubImmediate() argument
266 USE(instr); in VisitAddSubImmediate()
273 void Instrument::VisitLogicalImmediate(const Instruction* instr) { in VisitLogicalImmediate() argument
274 USE(instr); in VisitLogicalImmediate()
281 void Instrument::VisitMoveWideImmediate(const Instruction* instr) { in VisitMoveWideImmediate() argument
285 if (instr->IsMovn() && (instr->GetRd() == kZeroRegCode)) { in VisitMoveWideImmediate()
286 unsigned imm = instr->GetImmMoveWide(); in VisitMoveWideImmediate()
294 void Instrument::VisitBitfield(const Instruction* instr) { in VisitBitfield() argument
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Dcpu-features-auditor-aarch64.cc80 void CPUFeaturesAuditor::LoadStoreHelper(const Instruction* instr) { in LoadStoreHelper() argument
82 switch (instr->Mask(LoadStoreMask)) { in LoadStoreHelper()
103 void CPUFeaturesAuditor::LoadStorePairHelper(const Instruction* instr) { in LoadStorePairHelper() argument
105 switch (instr->Mask(LoadStorePairMask)) { in LoadStorePairHelper()
123 void CPUFeaturesAuditor::VisitAddSubExtended(const Instruction* instr) { in VisitAddSubExtended() argument
125 USE(instr); in VisitAddSubExtended()
128 void CPUFeaturesAuditor::VisitAddSubImmediate(const Instruction* instr) { in VisitAddSubImmediate() argument
130 USE(instr); in VisitAddSubImmediate()
133 void CPUFeaturesAuditor::VisitAddSubShifted(const Instruction* instr) { in VisitAddSubShifted() argument
135 USE(instr); in VisitAddSubShifted()
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Ddisasm-aarch64.cc64 void Disassembler::VisitAddSubImmediate(const Instruction *instr) { in VisitAddSubImmediate() argument
65 bool rd_is_zr = RdIsZROrSP(instr); in VisitAddSubImmediate()
67 (rd_is_zr || RnIsZROrSP(instr)) && (instr->GetImmAddSub() == 0) ? true in VisitAddSubImmediate()
74 switch (instr->Mask(AddSubImmediateMask)) { in VisitAddSubImmediate()
109 Format(instr, mnemonic, form); in VisitAddSubImmediate()
113 void Disassembler::VisitAddSubShifted(const Instruction *instr) { in VisitAddSubShifted() argument
114 bool rd_is_zr = RdIsZROrSP(instr); in VisitAddSubShifted()
115 bool rn_is_zr = RnIsZROrSP(instr); in VisitAddSubShifted()
121 switch (instr->Mask(AddSubShiftedMask)) { in VisitAddSubShifted()
159 Format(instr, mnemonic, form); in VisitAddSubShifted()
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/external/v8/src/arm64/
Ddecoder-arm64-inl.h19 void Decoder<V>::Decode(Instruction *instr) { in Decode() argument
20 if (instr->Bits(28, 27) == 0) { in Decode()
21 V::VisitUnallocated(instr); in Decode()
23 switch (instr->Bits(27, 24)) { in Decode()
25 case 0x0: DecodePCRelAddressing(instr); break; in Decode()
28 case 0x1: DecodeAddSubImmediate(instr); break; in Decode()
41 case 0xB: DecodeDataProcessing(instr); break; in Decode()
45 case 0x2: DecodeLogical(instr); break; in Decode()
49 case 0x3: DecodeBitfieldExtract(instr); break; in Decode()
62 case 0x7: DecodeBranchSystemException(instr); break; in Decode()
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Ddisasm-arm64.cc49 void DisassemblingDecoder::VisitAddSubImmediate(Instruction* instr) { in VisitAddSubImmediate() argument
50 bool rd_is_zr = RdIsZROrSP(instr); in VisitAddSubImmediate()
51 bool stack_op = (rd_is_zr || RnIsZROrSP(instr)) && in VisitAddSubImmediate()
52 (instr->ImmAddSub() == 0) ? true : false; in VisitAddSubImmediate()
58 switch (instr->Mask(AddSubImmediateMask)) { in VisitAddSubImmediate()
90 Format(instr, mnemonic, form); in VisitAddSubImmediate()
94 void DisassemblingDecoder::VisitAddSubShifted(Instruction* instr) { in VisitAddSubShifted() argument
95 bool rd_is_zr = RdIsZROrSP(instr); in VisitAddSubShifted()
96 bool rn_is_zr = RnIsZROrSP(instr); in VisitAddSubShifted()
102 switch (instr->Mask(AddSubShiftedMask)) { in VisitAddSubShifted()
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Dinstrument-arm64.cc232 void Instrument::VisitPCRelAddressing(Instruction* instr) { in VisitPCRelAddressing() argument
239 void Instrument::VisitAddSubImmediate(Instruction* instr) { in VisitAddSubImmediate() argument
246 void Instrument::VisitLogicalImmediate(Instruction* instr) { in VisitLogicalImmediate() argument
253 void Instrument::VisitMoveWideImmediate(Instruction* instr) { in VisitMoveWideImmediate() argument
257 if (instr->IsMovn() && (instr->Rd() == kZeroRegCode)) { in VisitMoveWideImmediate()
258 unsigned imm = instr->ImmMoveWide(); in VisitMoveWideImmediate()
266 void Instrument::VisitBitfield(Instruction* instr) { in VisitBitfield() argument
273 void Instrument::VisitExtract(Instruction* instr) { in VisitExtract() argument
280 void Instrument::VisitUnconditionalBranch(Instruction* instr) { in VisitUnconditionalBranch() argument
287 void Instrument::VisitUnconditionalBranchToRegister(Instruction* instr) { in VisitUnconditionalBranchToRegister() argument
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/external/v8/src/mips64/
Ddisasm-mips64.cc73 void PrintRs(Instruction* instr);
74 void PrintRt(Instruction* instr);
75 void PrintRd(Instruction* instr);
76 void PrintFs(Instruction* instr);
77 void PrintFt(Instruction* instr);
78 void PrintFd(Instruction* instr);
79 void PrintSa(Instruction* instr);
80 void PrintLsaSa(Instruction* instr);
81 void PrintSd(Instruction* instr);
82 void PrintSs1(Instruction* instr);
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/external/v8/src/arm/
Ddisasm-arm.cc78 int FormatVFPRegister(Instruction* instr, const char* format);
79 void PrintMovwMovt(Instruction* instr);
80 int FormatVFPinstruction(Instruction* instr, const char* format);
81 void PrintCondition(Instruction* instr);
82 void PrintShiftRm(Instruction* instr);
83 void PrintShiftImm(Instruction* instr);
84 void PrintShiftSat(Instruction* instr);
85 void PrintPU(Instruction* instr);
89 int FormatRegister(Instruction* instr, const char* option);
92 int FormatOption(Instruction* instr, const char* option);
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/external/v8/src/mips/
Ddisasm-mips.cc72 void PrintRs(Instruction* instr);
73 void PrintRt(Instruction* instr);
74 void PrintRd(Instruction* instr);
75 void PrintFs(Instruction* instr);
76 void PrintFt(Instruction* instr);
77 void PrintFd(Instruction* instr);
78 void PrintSa(Instruction* instr);
79 void PrintLsaSa(Instruction* instr);
80 void PrintSd(Instruction* instr);
81 void PrintSs1(Instruction* instr);
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/external/vixl/src/aarch32/
Ddisasm-aarch32.cc55 T32CodeAddressIncrementer(uint32_t instr, uint32_t* code_address) in T32CodeAddressIncrementer() argument
57 increment_(Disassembler::Is16BitEncoding(instr) ? 2 : 4) {} in T32CodeAddressIncrementer()
6974 int Disassembler::T32Size(uint32_t instr) { in T32Size() argument
6975 if ((instr & 0xe0000000) == 0xe0000000) { in T32Size()
6976 switch (instr & 0x08000000) { in T32Size()
6978 if ((instr & 0x10000000) == 0x10000000) return 4; in T32Size()
6989 void Disassembler::DecodeT32(uint32_t instr) { in DecodeT32() argument
6990 T32CodeAddressIncrementer incrementer(instr, &code_address_); in DecodeT32()
6993 switch (instr & 0xe0000000) { in DecodeT32()
6996 switch (instr & 0x18000000) { in DecodeT32()
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/external/v8/src/ppc/
Ddisasm-ppc.cc70 int FormatFPRegister(Instruction* instr, const char* format);
74 int FormatRegister(Instruction* instr, const char* option);
75 int FormatOption(Instruction* instr, const char* option);
76 void Format(Instruction* instr, const char* format);
77 void Unknown(Instruction* instr);
78 void UnknownFormat(Instruction* instr, const char* opcname);
80 void DecodeExt1(Instruction* instr);
81 void DecodeExt2(Instruction* instr);
82 void DecodeExt3(Instruction* instr);
83 void DecodeExt4(Instruction* instr);
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/external/v8/src/s390/
Ddisasm-s390.cc71 int FormatRegister(Instruction* instr, const char* option);
72 int FormatFloatingRegister(Instruction* instr, const char* option);
73 int FormatMask(Instruction* instr, const char* option);
74 int FormatDisplacement(Instruction* instr, const char* option);
75 int FormatImmediate(Instruction* instr, const char* option);
76 int FormatOption(Instruction* instr, const char* option);
77 void Format(Instruction* instr, const char* format);
78 void Unknown(Instruction* instr);
79 void UnknownFormat(Instruction* instr, const char* opcname);
81 bool DecodeSpecial(Instruction* instr);
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/external/mesa3d/src/gallium/drivers/freedreno/ir3/
Dir3.c121 static int emit_cat0(struct ir3_instruction *instr, void *ptr, in emit_cat0() argument
127 cat0->a5xx.immed = instr->cat0.immed; in emit_cat0()
129 cat0->a4xx.immed = instr->cat0.immed; in emit_cat0()
131 cat0->a3xx.immed = instr->cat0.immed; in emit_cat0()
133 cat0->repeat = instr->repeat; in emit_cat0()
134 cat0->ss = !!(instr->flags & IR3_INSTR_SS); in emit_cat0()
135 cat0->inv = instr->cat0.inv; in emit_cat0()
136 cat0->comp = instr->cat0.comp; in emit_cat0()
137 cat0->opc = instr->opc; in emit_cat0()
138 cat0->jmp_tgt = !!(instr->flags & IR3_INSTR_JP); in emit_cat0()
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Dir3_group.c43 void (*insert_mov)(void *arr, int idx, struct ir3_instruction *instr);
50 static void arr_insert_mov_out(void *arr, int idx, struct ir3_instruction *instr) in arr_insert_mov_out() argument
53 ir3_MOV(instr->block, instr, TYPE_F32); in arr_insert_mov_out()
55 static void arr_insert_mov_in(void *arr, int idx, struct ir3_instruction *instr) in arr_insert_mov_in() argument
64 debug_assert(instr->regs_count == 1); in arr_insert_mov_in()
66 in = ir3_instr_create(instr->block, OPC_META_INPUT); in arr_insert_mov_in()
67 in->inout.block = instr->block; in arr_insert_mov_in()
68 ir3_reg_create(in, instr->regs[0]->num, 0); in arr_insert_mov_in()
71 ir3_reg_create(instr, 0, IR3_REG_SSA)->instr = in; in arr_insert_mov_in()
72 instr->opc = OPC_MOV; in arr_insert_mov_in()
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Dir3_sched.c63 static bool is_sfu_or_mem(struct ir3_instruction *instr) in is_sfu_or_mem() argument
65 return is_sfu(instr) || is_mem(instr); in is_sfu_or_mem()
71 clear_cache(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr) in clear_cache() argument
74 if ((instr2->data == instr) || (instr2->data == NULL_INSTR) || !instr) in clear_cache()
80 schedule(struct ir3_sched_ctx *ctx, struct ir3_instruction *instr) in schedule() argument
82 debug_assert(ctx->block == instr->block); in schedule()
88 if (ctx->scheduled && is_sfu_or_mem(ctx->scheduled) && is_sfu_or_mem(instr)) in schedule()
93 list_delinit(&instr->node); in schedule()
95 if (writes_addr(instr)) { in schedule()
97 ctx->addr = instr; in schedule()
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Dir3_cp.c45 static bool is_eligible_mov(struct ir3_instruction *instr, bool allow_flags) in is_eligible_mov() argument
47 if (is_same_type_mov(instr)) { in is_eligible_mov()
48 struct ir3_register *dst = instr->regs[0]; in is_eligible_mov()
49 struct ir3_register *src = instr->regs[1]; in is_eligible_mov()
92 static bool valid_flags(struct ir3_instruction *instr, unsigned n, in valid_flags() argument
101 if ((instr->regs[0]->flags & IR3_REG_RELATIV) && in valid_flags()
114 switch (opc_cat(instr->opc)) { in valid_flags()
121 valid_flags = ir3_cat2_absneg(instr->opc) | in valid_flags()
124 if (ir3_cat2_int(instr->opc)) in valid_flags()
135 if (m < instr->regs_count) { in valid_flags()
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Dir3.h120 struct ir3_instruction *instr; member
372 ir3_neighbor_first(struct ir3_instruction *instr) in ir3_neighbor_first() argument
375 while (instr->cp.left) { in ir3_neighbor_first()
376 instr = instr->cp.left; in ir3_neighbor_first()
382 return instr; in ir3_neighbor_first()
385 static inline int ir3_neighbor_count(struct ir3_instruction *instr) in ir3_neighbor_count() argument
389 debug_assert(!instr->cp.left); in ir3_neighbor_count()
391 while (instr->cp.right) { in ir3_neighbor_count()
393 instr = instr->cp.right; in ir3_neighbor_count()
526 struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr);
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Dir3_print.c36 static void print_instr_name(struct ir3_instruction *instr) in print_instr_name() argument
38 if (!instr) in print_instr_name()
41 printf("%04u:", instr->serialno); in print_instr_name()
43 printf("%04u:", instr->name); in print_instr_name()
44 printf("%03u: ", instr->depth); in print_instr_name()
46 if (instr->flags & IR3_INSTR_SY) in print_instr_name()
48 if (instr->flags & IR3_INSTR_SS) in print_instr_name()
51 if (is_meta(instr)) { in print_instr_name()
52 switch(instr->opc) { in print_instr_name()
58 switch (instr->opc) { in print_instr_name()
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/external/tensorflow/tensorflow/compiler/xla/service/gpu/
Dgpu_fusible.cc31 void AppendParams(const HloInstruction& instr, in AppendParams() argument
33 if (instr.opcode() == HloOpcode::kFusion) { in AppendParams()
34 params->insert(std::end(*params), std::begin(instr.fused_parameters()), in AppendParams()
35 std::end(instr.fused_parameters())); in AppendParams()
37 for (HloInstruction* operand : instr.operands()) { in AppendParams()
63 bool IsReduceInputFusion(const HloInstruction& instr) { in IsReduceInputFusion() argument
64 if (instr.IsMultiOutputFusion()) { in IsReduceInputFusion()
66 instr.fused_expression_root()->operands()) { in IsReduceInputFusion()
68 CHECK(instr.fusion_kind() == HloInstruction::FusionKind::kInput) in IsReduceInputFusion()
71 << instr.ToString(); in IsReduceInputFusion()
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/external/mesa3d/src/broadcom/qpu/
Dqpu_disasm.c60 const struct v3d_qpu_instr *instr, uint8_t mux) in v3d_qpu_disasm_raddr() argument
63 append(disasm, "rf%d", instr->raddr_a); in v3d_qpu_disasm_raddr()
65 if (instr->sig.small_imm) { in v3d_qpu_disasm_raddr()
69 instr->raddr_b, in v3d_qpu_disasm_raddr()
78 append(disasm, "rf%d", instr->raddr_b); in v3d_qpu_disasm_raddr()
102 const struct v3d_qpu_instr *instr) in v3d_qpu_disasm_add() argument
104 bool has_dst = v3d_qpu_add_op_has_dst(instr->alu.add.op); in v3d_qpu_disasm_add()
105 int num_src = v3d_qpu_add_op_num_src(instr->alu.add.op); in v3d_qpu_disasm_add()
107 append(disasm, "%s", v3d_qpu_add_op_name(instr->alu.add.op)); in v3d_qpu_disasm_add()
108 if (!v3d_qpu_sig_writes_address(disasm->devinfo, &instr->sig)) in v3d_qpu_disasm_add()
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/external/mesa3d/src/compiler/nir/
Dnir_opt_constant_folding.c42 constant_fold_alu_instr(nir_alu_instr *instr, void *mem_ctx) in constant_fold_alu_instr() argument
46 if (!instr->dest.dest.is_ssa) in constant_fold_alu_instr()
59 if (!nir_alu_type_get_type_size(nir_op_infos[instr->op].output_type)) in constant_fold_alu_instr()
60 bit_size = instr->dest.dest.ssa.bit_size; in constant_fold_alu_instr()
62 for (unsigned i = 0; i < nir_op_infos[instr->op].num_inputs; i++) { in constant_fold_alu_instr()
63 if (!instr->src[i].src.is_ssa) in constant_fold_alu_instr()
67 !nir_alu_type_get_type_size(nir_op_infos[instr->op].input_sizes[i])) { in constant_fold_alu_instr()
68 bit_size = instr->src[i].src.ssa->bit_size; in constant_fold_alu_instr()
71 nir_instr *src_instr = instr->src[i].src.ssa->parent_instr; in constant_fold_alu_instr()
77 for (unsigned j = 0; j < nir_ssa_alu_instr_src_components(instr, i); in constant_fold_alu_instr()
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Dnir_lower_alu_to_scalar.c34 nir_alu_ssa_dest_init(nir_alu_instr *instr, unsigned num_components, in nir_alu_ssa_dest_init() argument
37 nir_ssa_dest_init(&instr->instr, &instr->dest.dest, num_components, in nir_alu_ssa_dest_init()
39 instr->dest.write_mask = (1 << num_components) - 1; in nir_alu_ssa_dest_init()
43 lower_reduction(nir_alu_instr *instr, nir_op chan_op, nir_op merge_op, in lower_reduction() argument
46 unsigned num_components = nir_op_infos[instr->op].input_sizes[0]; in lower_reduction()
51 nir_alu_ssa_dest_init(chan, 1, instr->dest.dest.ssa.bit_size); in lower_reduction()
52 nir_alu_src_copy(&chan->src[0], &instr->src[0], chan); in lower_reduction()
56 nir_alu_src_copy(&chan->src[1], &instr->src[1], chan); in lower_reduction()
59 chan->exact = instr->exact; in lower_reduction()
61 nir_builder_instr_insert(builder, &chan->instr); in lower_reduction()
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Dnir_opt_gcm.c61 nir_instr *instr; member
111 nir_foreach_instr_safe(instr, block) { in gcm_pin_instructions_block()
112 switch (instr->type) { in gcm_pin_instructions_block()
114 switch (nir_instr_as_alu(instr)->op) { in gcm_pin_instructions_block()
122 instr->pass_flags = GCM_INSTR_PINNED; in gcm_pin_instructions_block()
126 instr->pass_flags = 0; in gcm_pin_instructions_block()
132 switch (nir_instr_as_tex(instr)->op) { in gcm_pin_instructions_block()
137 instr->pass_flags = GCM_INSTR_PINNED; in gcm_pin_instructions_block()
141 instr->pass_flags = 0; in gcm_pin_instructions_block()
147 instr->pass_flags = 0; in gcm_pin_instructions_block()
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Dnir_instr_set.c51 hash_alu(uint32_t hash, const nir_alu_instr *instr) in hash_alu() argument
53 hash = HASH(hash, instr->op); in hash_alu()
54 hash = HASH(hash, instr->dest.dest.ssa.num_components); in hash_alu()
55 hash = HASH(hash, instr->dest.dest.ssa.bit_size); in hash_alu()
58 if (nir_op_infos[instr->op].algebraic_properties & NIR_OP_IS_COMMUTATIVE) { in hash_alu()
59 assert(nir_op_infos[instr->op].num_inputs == 2); in hash_alu()
60 uint32_t hash0 = hash_alu_src(hash, &instr->src[0], in hash_alu()
61 nir_ssa_alu_instr_src_components(instr, 0)); in hash_alu()
62 uint32_t hash1 = hash_alu_src(hash, &instr->src[1], in hash_alu()
63 nir_ssa_alu_instr_src_components(instr, 1)); in hash_alu()
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