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Searched refs:isPred (Results 1 – 13 of 13) sorted by relevance

/external/swiftshader/third_party/LLVM/lib/CodeGen/
DRegisterScavenging.cpp150 bool isPred = TII->isPredicated(MI); in forward() local
168 if (!isPred && (MO.isKill() || MI->isRegTiedToDefOperand(i))) in forward()
172 if (!isPred && MO.isDead()) in forward()
DScheduleDAGInstrs.cpp512 if (!ExitSU.isPred(SU)) in BuildSchedGraph()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DMacroFusion.cpp81 SU == &DAG.ExitSU || SU == &SecondSU || SU->isPred(&SecondSU)) in fuseInstructionPair()
DMachinePipeliner.cpp1199 if (SU->NodeNum < I.NodeNum && !I.isPred(SU)) in updatePhiDependences()
1220 if (SU->NodeNum < I.NodeNum && !I.isPred(SU)) in updatePhiDependences()
1622 static bool ignoreDependence(const SDep &D, bool isPred) { in ignoreDependence() argument
1625 return D.getKind() == SDep::Anti && isPred; in ignoreDependence()
3743 !SU->isPred(I)) in computeStart()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DHexagonPseudo.td202 class Call_nr<bits<5> nbits, bit isPred, bit isFalse, dag iops,
208 let isPredicable = 0; // !if(isPred, 0, 1);
209 let isPredicated = 0; // isPred;
/external/swiftshader/third_party/LLVM/lib/Target/ARM/
DThumb2SizeReduction.cpp757 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate()); in ReduceToNarrow() local
758 if (SkipPred && isPred) in ReduceToNarrow()
/external/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp900 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate()); in ReduceToNarrow() local
901 if (SkipPred && isPred) in ReduceToNarrow()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/
DThumb2SizeReduction.cpp923 bool isPred = (i < NumOps && MCID.OpInfo[i].isPredicate()); in ReduceToNarrow() local
924 if (SkipPred && isPred) in ReduceToNarrow()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DScheduleDAG.h436 bool isPred(const SUnit *N) const {
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DScheduleDAG.h397 bool isPred(SUnit *N) {
/external/llvm/include/llvm/CodeGen/
DScheduleDAG.h452 bool isPred(SUnit *N) {
/external/llvm/lib/CodeGen/
DMachinePipeliner.cpp1109 if (SU->NodeNum < I.NodeNum && !I.isPred(SU)) in updatePhiDependences()
1130 if (SU->NodeNum < I.NodeNum && !I.isPred(SU)) in updatePhiDependences()
1510 static bool ignoreDependence(const SDep &D, bool isPred) { in ignoreDependence() argument
1513 return D.getKind() == SDep::Anti && isPred; in ignoreDependence()
3598 !SU->isPred(I)) in computeStart()
/external/llvm/lib/Target/Hexagon/
DHexagonInstrInfo.td1555 class JUMPR_MISC_CALLR<bit isPred, bit isPredNot,
1558 !if(isPred, !if(isPredNot, "if (!$Pu) callr $Rs",
1564 let isPredicated = isPred;
1569 let Inst{24-23} = !if (isPred, 0b10, 0b01);
1572 let Inst{9-8} = !if (isPred, Pu, 0b00);