Searched refs:isRegSequence (Results 1 – 25 of 41) sorted by relevance
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289 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), in optimizeSDPattern()335 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass)) in hasPartialWrite()399 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
295 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), in optimizeSDPattern()341 if (MI->isRegSequence() && usesRegClass(MI->getOperand(1), &ARM::SPRRegClass)) in hasPartialWrite()405 if (MI->isCopyLike() || MI->isInsertSubreg() || MI->isRegSequence() || in getReadDPRs()
66 !MI->isRegSequence() && in canTurnIntoImplicitDef()
241 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()1019 assert(MI.isRegSequence() && "Invalid instruction"); in RegSequenceRewriter()1871 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()2061 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
1156 assert((MI.isRegSequence() || in getRegSequenceInputs()1159 if (!MI.isRegSequence()) in getRegSequenceInputs()
68 !MI->isRegSequence() && in canTurnIntoImplicitDef()
198 (MI.isRegSequence() || MI.isInsertSubreg() || in isCoalescableCopy()1083 assert(MI.isRegSequence() && "Invalid instruction"); in RegSequenceRewriter()1716 assert((Def->isRegSequence() || Def->isRegSequenceLike()) && in getNextSourceFromRegSequence()1902 if (Def->isRegSequence() || Def->isRegSequenceLike()) in getNextSourceImpl()
1126 assert((MI.isRegSequence() || in getRegSequenceInputs()1129 if (!MI.isRegSequence()) in getRegSequenceInputs()
135 FLAG(isRegSequence) in EmitInstrDocs()
258 bool isRegSequence : 1; variable
603 if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)"; in emitRecord()
327 isRegSequence = R->getValueAsBit("isRegSequence"); in CodeGenInstruction()
255 bool isRegSequence : 1; variable
506 if (Inst.isRegSequence) OS << "|(1ULL<<MCID::RegSequence)"; in emitRecord()
323 isRegSequence = R->getValueAsBit("isRegSequence"); in CodeGenInstruction()
180 assert(MI.isRegSequence()); in foldVGPRCopyIntoRegSequence()
338 if (isRegSequence() && OpIdx > 1 && (OpIdx % 2) == 0)884 bool isRegSequence() const {
281 bool isRegSequence() const {
382 return MI->isInsertSubreg() || MI->isSubregToReg() || MI->isRegSequence(); in AvoidsSinking()
1079 if (mi->isRegSequence()) in runOnMachineFunction()1422 if (UseMI != RegSeq && UseMI->isRegSequence()) in HasOtherRegSequenceUses()
347 if ((DstInst->isRegSequence() || DstInst->isCopy()) && Dst->NumSuccs == 1) { in adjustSchedDependency()
237 assert(MI.isRegSequence()); in foldVGPRCopyIntoRegSequence()
343 if (UseMI->isRegSequence()) { in foldOperand()
271 return !MI.isInsertSubreg() && !MI.isSubregToReg() && !MI.isRegSequence(); in shouldSink()
811 bool isRegSequence() const {