| /external/mesa3d/src/intel/isl/ |
| D | isl_storage_image.c | 111 devinfo->gen >= 8 || devinfo->is_haswell ? in isl_lower_storage_image_format()
128 devinfo->gen >= 8 || devinfo->is_haswell ? in isl_lower_storage_image_format()
135 devinfo->gen >= 8 || devinfo->is_haswell ? in isl_lower_storage_image_format()
141 devinfo->gen >= 8 || devinfo->is_haswell ? in isl_lower_storage_image_format()
164 return (devinfo->gen >= 8 || devinfo->is_haswell ? in isl_lower_storage_image_format()
170 return (devinfo->gen >= 8 || devinfo->is_haswell ? in isl_lower_storage_image_format()
175 return (devinfo->gen >= 8 || devinfo->is_haswell ? in isl_lower_storage_image_format()
180 return (devinfo->gen >= 8 || devinfo->is_haswell ? in isl_lower_storage_image_format()
203 } else if (devinfo->gen >= 8 || devinfo->is_haswell) { in isl_has_matching_typed_storage_image_format()
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| /external/mesa3d/src/intel/compiler/ |
| D | brw_vec4_surface_builder.cpp | 185 bld.shader->devinfo->is_haswell); in emit_untyped_write()
207 bld.shader->devinfo->is_haswell); in emit_untyped_atomic()
246 !bld.shader->devinfo->is_haswell) { in emit_typed_message_header()
268 bld.shader->devinfo->is_haswell); in emit_typed_read()
292 bld.shader->devinfo->is_haswell); in emit_typed_write()
315 bld.shader->devinfo->is_haswell); in emit_typed_atomic()
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| D | brw_eu_emit.c | 254 } else if (devinfo->gen == 7 && !devinfo->is_haswell && in brw_set_src0()
344 } else if (devinfo->gen == 7 && !devinfo->is_haswell && in brw_set_src1()
989 if (devinfo->gen == 7 && !devinfo->is_haswell && in ALU1()
2420 assert(devinfo->is_haswell || devinfo->gen >= 8); in brw_adjust_sampler_state_pointer()
2428 if (devinfo->gen < 8 && !devinfo->is_haswell) { in brw_adjust_sampler_state_pointer()
2851 if (devinfo->gen >= 8 || devinfo->is_haswell) { in brw_set_dp_untyped_atomic_message()
2883 const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ? in brw_untyped_atomic()
2897 devinfo->gen >= 8 || devinfo->is_haswell, true), in brw_untyped_atomic()
2921 (devinfo->gen >= 8 || devinfo->is_haswell ? in brw_set_dp_untyped_surface_read_message()
2936 const unsigned sfid = (devinfo->gen >= 8 || devinfo->is_haswell ? in brw_untyped_surface_read()
[all …]
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| D | brw_schedule_instructions.cpp | 67 void set_latency_gen7(bool is_haswell);
156 schedule_node::set_latency_gen7(bool is_haswell) in set_latency_gen7() argument
182 latency = is_haswell ? 16 : 18; in set_latency_gen7()
227 latency = is_haswell ? 14 : 16; in set_latency_gen7()
238 latency = is_haswell ? 22 : 24; in set_latency_gen7()
413 latency = is_haswell ? 300 : 600; in set_latency_gen7()
808 set_latency_gen7(devinfo->is_haswell); in schedule_node()
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| D | brw_eu_validate.c | 458 if (devinfo->gen == 7 && !devinfo->is_haswell && in general_restrictions_based_on_operand_types()
516 if (devinfo->is_haswell || devinfo->gen >= 8) { in general_restrictions_on_region_parameters()
531 if (devinfo->is_haswell || devinfo->gen >= 8) { in general_restrictions_on_region_parameters()
575 if (devinfo->gen == 7 && !devinfo->is_haswell && in general_restrictions_on_region_parameters()
800 if (devinfo->gen == 7 && !devinfo->is_haswell && in region_alignment_rules()
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| D | brw_fs_generator.cpp | 97 if (devinfo->gen == 7 && !devinfo->is_haswell) { in brw_reg_from_fs_reg()
164 if (devinfo->gen == 7 && !devinfo->is_haswell && in brw_reg_from_fs_reg()
317 if (devinfo->gen < 8 && !devinfo->is_haswell) { in generate_fb_write()
500 ((devinfo->gen == 7 && !devinfo->is_haswell) || in generate_mov_indirect()
812 assert(devinfo->gen >= 8 || devinfo->is_haswell); in generate_tex()
1709 if (devinfo->gen == 7 && !devinfo->is_haswell && in generate_code()
1799 if (inst->exec_size >= 16 && devinfo->gen == 7 && !devinfo->is_haswell && in generate_code()
2168 assert(devinfo->is_haswell); in generate_code()
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| D | brw_nir_analyze_ubo_ranges.c | 174 if ((devinfo->gen <= 7 && !devinfo->is_haswell) || in brw_nir_analyze_ubo_ranges()
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| D | brw_fs_surface_builder.cpp | 360 return (devinfo->gen == 7 && !devinfo->is_haswell && in has_undefined_high_bits()
388 if (devinfo->gen == 7 && !devinfo->is_haswell) { in emit_untyped_image_check()
419 if (devinfo->gen == 7 && !devinfo->is_haswell) { in emit_typed_atomic_check()
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| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| D | gen7_urb.c | 75 (devinfo->gen >= 8 || (devinfo->is_haswell && devinfo->gt == 3)) ? 2 : 1; in gen7_allocate_push_constants()
149 if (devinfo->gen < 8 && !devinfo->is_haswell && !devinfo->is_baytrail) in gen7_emit_push_constant_state()
184 (devinfo->gen >= 8 || (devinfo->is_haswell && devinfo->gt == 3)) ? 32 : 16; in gen7_upload_urb()
227 if (devinfo->gen == 7 && !devinfo->is_haswell && !devinfo->is_baytrail) in gen7_upload_urb()
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| D | brw_draw_upload.c | 257 devinfo->gen <= 7 && !devinfo->is_baytrail && !devinfo->is_haswell; in brw_get_vertex_surface_type()
318 if (devinfo->gen >= 8 || devinfo->is_haswell) in brw_get_vertex_surface_type()
332 if (devinfo->gen >= 8 || devinfo->is_haswell) { in brw_get_vertex_surface_type()
340 if (devinfo->gen >= 8 || devinfo->is_haswell) { in brw_get_vertex_surface_type()
357 if (devinfo->gen >= 8 || devinfo->is_haswell) { in brw_get_vertex_surface_type()
365 if (devinfo->gen >= 8 || devinfo->is_haswell) { in brw_get_vertex_surface_type()
389 if (devinfo->gen >= 8 || devinfo->is_haswell) in brw_get_vertex_surface_type()
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| D | intel_extensions.c | 142 else if (devinfo->is_haswell && can_do_pipelined_register_writes(brw->screen)) in intelInitExtensions()
247 devinfo->gen >= 8 || devinfo->is_haswell; in intelInitExtensions()
257 if (devinfo->gen >= 8 || devinfo->is_haswell) { in intelInitExtensions()
265 if (devinfo->gen >= 8 || devinfo->is_haswell || devinfo->is_baytrail) { in intelInitExtensions()
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| D | hsw_sol.c | 201 if (devinfo->is_haswell) { in hsw_pause_transform_feedback()
231 if (devinfo->is_haswell) { in hsw_resume_transform_feedback()
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| D | brw_pipe_control.c | 76 if (devinfo->gen == 7 && !devinfo->is_haswell) { in gen7_cs_stall_every_four_pipe_controls()
485 if (devinfo->is_haswell) { in brw_emit_end_of_pipe_sync()
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| D | brw_primitive_restart.c | 86 if (devinfo->gen >= 8 || devinfo->is_haswell) in can_cut_index_handle_prims()
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| D | brw_program.c | 309 if (devinfo->gen == 7 && !devinfo->is_haswell) in brw_memory_barrier()
406 if (devinfo->is_haswell) { in brw_alloc_stage_scratch()
735 const bool has_shader_channel_select = devinfo->is_haswell || devinfo->gen >= 8; in brw_setup_tex_for_precompile()
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| D | brw_wm.c | 317 if (alpha_depth || (devinfo->gen < 8 && !devinfo->is_haswell)) in brw_populate_sampler_prog_key_data()
346 devinfo->is_haswell ? t->_Swizzle : key->swizzles[s]; in brw_populate_sampler_prog_key_data()
361 if (!devinfo->is_haswell) in brw_populate_sampler_prog_key_data()
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| D | gen7_misc_state.c | 165 const int enabled = devinfo->is_haswell ? HSW_STENCIL_ENABLED : 0; in gen7_emit_depth_stencil_hiz()
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| D | intel_screen.c | 1982 if (screen->cmd_parser_version >= (devinfo->is_haswell ? 7 : 2)) in intel_detect_pipelined_so()
2255 if (screen->devinfo.is_haswell && can_do_compute_dispatch(screen)) in set_max_gl_versions()
2257 if (screen->devinfo.is_haswell && can_do_mi_math_and_lrr(screen)) in set_max_gl_versions()
2262 dri_screen->max_gl_es2_version = screen->devinfo.is_haswell ? 31 : 30; in set_max_gl_versions()
2627 if (devinfo->is_haswell && screen->cmd_parser_version >= 4) { in intelInitScreen2()
2637 (devinfo->is_haswell && screen->cmd_parser_version >= 7)) { in intelInitScreen2()
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| D | gen7_l3_state.c | 152 OUT_BATCH((devinfo->is_haswell ? HSW_L3SQCREG1_SQGHPCI_DEFAULT : in setup_l3_config()
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| D | brw_performance_query.c | 1697 if (devinfo->is_haswell || devinfo->gen == 8) in init_pipeline_statistic_query_registers()
1929 if (devinfo->is_haswell) { in init_oa_sys_vars()
2072 if (devinfo->is_haswell) in get_register_queries_function()
2131 if (devinfo->is_haswell) in brw_init_perf_query_info()
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| D | gen6_constant_state.c | 153 if (devinfo->gen >= 8 || devinfo->is_haswell) { in gen6_upload_push_constants()
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| D | intel_batchbuffer.c | 750 if (devinfo->is_haswell) { in brw_finish_batch()
1341 assert(brw->screen->devinfo.gen >= 8 || brw->screen->devinfo.is_haswell); in brw_load_register_reg()
1356 assert(brw->screen->devinfo.gen >= 8 || brw->screen->devinfo.is_haswell); in brw_load_register_reg64()
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| D | brw_vs.c | 325 if (devinfo->gen < 8 && !devinfo->is_haswell) { in brw_vs_populate_key()
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| /external/mesa3d/src/intel/common/ |
| D | gen_device_info.h | 46 bool is_haswell; member
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| /external/mesa3d/src/intel/vulkan/ |
| D | genX_query.c | 261 if ((device->info.gen == 8 || device->info.is_haswell) && in genX()
770 cmd_buffer->device->info.is_haswell) && in genX()
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