| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | armv8.1a-lor.s | 10 ldlar w0,[x1]
11 ldlar x0,[x1]
|
| /external/llvm/test/MC/AArch64/ |
| D | armv8.1a-lor.s | 10 ldlar w0,[x1]
11 ldlar x0,[x1]
|
| /external/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-lor.txt | 13 # CHECK: ldlar w0, [x1]
14 # CHECK: ldlar x0, [x1]
|
| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AArch64/ |
| D | armv8.1a-lor.txt | 13 # CHECK: ldlar w0, [x1]
14 # CHECK: ldlar x0, [x1]
|
| /external/vixl/test/aarch64/ |
| D | test-disasm-aarch64.cc | 1980 COMPARE(ldlar(w24, MemOperand(x25)), "ldlar w24, [x25]"); in TEST()
1981 COMPARE(ldlar(w26, MemOperand(sp)), "ldlar w26, [sp]"); in TEST()
1982 COMPARE(ldlar(x27, MemOperand(x28)), "ldlar x27, [x28]"); in TEST()
1983 COMPARE(ldlar(x29, MemOperand(sp)), "ldlar x29, [sp]"); in TEST()
|
| D | test-cpu-features-aarch64.cc | 3454 TEST_LOREGIONS(ldlar_0, ldlar(w0, MemOperand(x1, 0)))
3455 TEST_LOREGIONS(ldlar_1, ldlar(x0, MemOperand(x1, 0)))
|
| /external/vixl/src/aarch64/ |
| D | assembler-aarch64.h | 1406 void ldlar(const Register& rt, const MemOperand& src);
|
| D | macro-assembler-aarch64.h | 1629 ldlar(rt, src); in Ldlar()
|
| D | assembler-aarch64.cc | 1563 void Assembler::ldlar(const Register& rt, const MemOperand& src) { in ldlar() function in vixl::aarch64::Assembler
|
| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2477 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
2478 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
|
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.td | 2758 def LDLARW : LoadAcquire <0b10, 1, 1, 0, 0, GPR32, "ldlar">;
2759 def LDLARX : LoadAcquire <0b11, 1, 1, 0, 0, GPR64, "ldlar">;
|
| /external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/AArch64/ |
| D | AArch64GenAsmMatcher.inc | 11868 "f1w\005ldlar\006ldlarb\006ldlarh\006ldnf1b\006ldnf1d\006ldnf1h\007ldnf1"
15112 …{ 2253 /* ldlar */, AArch64::LDLARW, Convert__Reg1_0__GPR64sp01_2, Feature_HasV8_1a, { MCK_GPR32, …
15113 …{ 2253 /* ldlar */, AArch64::LDLARX, Convert__Reg1_0__GPR64sp01_2, Feature_HasV8_1a, { MCK_GPR64, …
21581 …{ 2253 /* ldlar */, AArch64::LDLARW, Convert__Reg1_0__GPR64sp01_2, Feature_HasV8_1a, { MCK_GPR32, …
21582 …{ 2253 /* ldlar */, AArch64::LDLARX, Convert__Reg1_0__GPR64sp01_2, Feature_HasV8_1a, { MCK_GPR64, …
31195 { Feature_HasV8_1a, 2253 /* ldlar */, MCK_GPR64sp0, 4 /* 2 */ },
31196 { Feature_HasV8_1a, 2253 /* ldlar */, MCK_GPR64sp0, 4 /* 2 */ },
31197 { Feature_HasV8_1a, 2253 /* ldlar */, MCK_GPR64sp0, 4 /* 2 */ },
31198 { Feature_HasV8_1a, 2253 /* ldlar */, MCK_GPR64sp0, 4 /* 2 */ },
|