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Searched refs:llwpcb (Results 1 – 10 of 10) sorted by relevance

/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/X86/
Dlwp-x86_64.s3 llwpcb %rcx label
4 # CHECK: llwpcb %rcx
Dlwp.s4 llwpcb %ecx label
5 # CHECK: llwpcb %ecx
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/X86/
Dlwp-intrinsics.ll17 ; X86-NEXT: llwpcb %eax
22 ; X64-NEXT: llwpcb %rdi
24 tail call void @llvm.x86.llwpcb(i8 *%a0)
118 declare void @llvm.x86.llwpcb(i8*) nounwind
Dlwp-schedule.ll11 ; GENERIC-NEXT: llwpcb %rdi # sched: [100:0.33]
16 ; BDVER-NEXT: llwpcb %rdi
18 tail call void @llvm.x86.llwpcb(i8 *%a0)
174 declare void @llvm.x86.llwpcb(i8*) nounwind
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/X86/
Dx86-64.txt479 # CHECK: llwpcb %rax
Dx86-32.txt780 #CHECK: llwpcb %ecx
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrInfo.td2680 def LLWPCB : I<0x12, MRM0r, (outs), (ins GR32:$src), "llwpcb\t$src",
2685 def LLWPCB64 : I<0x12, MRM0r, (outs), (ins GR64:$src), "llwpcb\t$src",
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc6271 x86_llwpcb, // llvm.x86.llwpcb
DIntrinsicImpl.inc6297 "llvm.x86.llwpcb",
15175 3, // llvm.x86.llwpcb
/external/swiftshader/third_party/llvm-7.0/configs/common/lib/Target/X86/
DX86GenAsmMatcher.inc6601 "lldtw\006llwpcb\004lmsw\005lmsww\004lock\004lods\005lodsb\005lodsd\005l"
7959 { 4036 /* llwpcb */, X86::LLWPCB, Convert__Reg1_0, 0, { MCK_GR32 }, },
7960 { 4036 /* llwpcb */, X86::LLWPCB64, Convert__Reg1_0, 0, { MCK_GR64 }, },
22511 { 4036 /* llwpcb */, X86::LLWPCB, Convert__Reg1_0, 0, { MCK_GR32 }, },
22512 { 4036 /* llwpcb */, X86::LLWPCB64, Convert__Reg1_0, 0, { MCK_GR64 }, },