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Searched refs:mctl_ctl (Results 1 – 9 of 9) sorted by relevance

/external/u-boot/arch/arm/mach-sunxi/
Ddram_sunxi_dw.c20 struct sunxi_mctl_ctl_reg * const mctl_ctl = in mctl_phy_init() local
23 writel(val | PIR_INIT, &mctl_ctl->pir); in mctl_phy_init()
24 mctl_await_completion(&mctl_ctl->pgsr[0], PGSR_INIT_DONE, 0x1); in mctl_phy_init()
29 struct sunxi_mctl_ctl_reg * const mctl_ctl = in mctl_set_bit_delays() local
33 clrbits_le32(&mctl_ctl->pgcr[0], 1 << 26); in mctl_set_bit_delays()
39 &mctl_ctl->dx[i].bdlr[j]); in mctl_set_bit_delays()
43 &mctl_ctl->acbdlr[i]); in mctl_set_bit_delays()
48 writel(0x6 << 24, &mctl_ctl->dx[i].sdlr); in mctl_set_bit_delays()
51 setbits_le32(&mctl_ctl->pgcr[0], 1 << 26); in mctl_set_bit_delays()
269 struct sunxi_mctl_ctl_reg * const mctl_ctl = in mctl_h3_zq_calibration_quirk() local
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Ddram_sun8i_a33.c88 struct sunxi_mctl_ctl_reg * const mctl_ctl = in auto_set_timing_para() local
133 writel(MCTL_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
134 writel(MCTL_MR1, &mctl_ctl->mr1); in auto_set_timing_para()
135 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
136 writel(MCTL_MR3, &mctl_ctl->mr3); in auto_set_timing_para()
139 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
141 writel(reg_val, &mctl_ctl->dramtmg1); in auto_set_timing_para()
143 writel(reg_val, &mctl_ctl->dramtmg2); in auto_set_timing_para()
145 writel(reg_val, &mctl_ctl->dramtmg3); in auto_set_timing_para()
147 writel(reg_val, &mctl_ctl->dramtmg4); in auto_set_timing_para()
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Ddram_sun6i.c106 struct sunxi_mctl_ctl_reg *mctl_ctl; in mctl_channel_init() local
110 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
113 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL1_BASE; in mctl_channel_init()
117 writel(MCTL_MCMD_NOP, &mctl_ctl->mcmd); in mctl_channel_init()
118 mctl_await_completion(&mctl_ctl->mcmd, MCTL_MCMD_BUSY, 0); in mctl_channel_init()
146 writel(1, &mctl_ctl->dfitphyupdtype0); in mctl_channel_init()
199 writel(MCTL_SCTL_CONFIG, &mctl_ctl->sctl); in mctl_channel_init()
200 mctl_await_completion(&mctl_ctl->sstat, 0x07, 0x01); in mctl_channel_init()
203 writel(DRAM_CLK / 1000000, &mctl_ctl->togcnt1u); in mctl_channel_init()
205 writel(DRAM_CLK / 10000000, &mctl_ctl->togcnt100n); in mctl_channel_init()
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Ddram_sun8i_a83t.c87 struct sunxi_mctl_ctl_reg * const mctl_ctl = in auto_set_timing_para() local
134 writel(MCTL_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
135 writel(MCTL_MR1, &mctl_ctl->mr1); in auto_set_timing_para()
136 writel(MCTL_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
137 writel(MCTL_MR3, &mctl_ctl->mr3); in auto_set_timing_para()
139 writel(MCTL_LPDDR3_MR0, &mctl_ctl->mr0); in auto_set_timing_para()
140 writel(MCTL_LPDDR3_MR1, &mctl_ctl->mr1); in auto_set_timing_para()
141 writel(MCTL_LPDDR3_MR2, &mctl_ctl->mr2); in auto_set_timing_para()
142 writel(MCTL_LPDDR3_MR3, &mctl_ctl->mr3); in auto_set_timing_para()
171 writel(reg_val, &mctl_ctl->dramtmg0); in auto_set_timing_para()
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Ddram_sun9i.c185 struct sunxi_mctl_ctl_reg *mctl_ctl = in mctl_ctl_sched_init() local
189 writel(SCHED_CONFIG, &mctl_ctl->sched); in mctl_ctl_sched_init()
190 writel(PERFHPR0_CONFIG, &mctl_ctl->perfhpr0); in mctl_ctl_sched_init()
191 writel(PERFHPR1_CONFIG, &mctl_ctl->perfhpr1); in mctl_ctl_sched_init()
192 writel(PERFLPR0_CONFIG, &mctl_ctl->perflpr0); in mctl_ctl_sched_init()
193 writel(PERFLPR1_CONFIG, &mctl_ctl->perflpr1); in mctl_ctl_sched_init()
194 writel(PERFWR0_CONFIG, &mctl_ctl->perfwr0); in mctl_ctl_sched_init()
195 writel(PERFWR1_CONFIG, &mctl_ctl->perfwr1); in mctl_ctl_sched_init()
357 struct sunxi_mctl_ctl_reg *mctl_ctl; in mctl_channel_init() local
452 mctl_ctl = (struct sunxi_mctl_ctl_reg *)SUNXI_DRAM_CTL0_BASE; in mctl_channel_init()
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Ddram_sun8i_a23.c96 struct sunxi_mctl_ctl_reg * const mctl_ctl = in mctl_init() local
146 writel(0, &mctl_ctl->odtmap); in mctl_init()
152 &mctl_ctl->rfshctl0); in mctl_init()
158 &mctl_ctl->dramtmg0); in mctl_init()
163 &mctl_ctl->dramtmg1); in mctl_init()
169 &mctl_ctl->dramtmg2); in mctl_init()
173 &mctl_ctl->dramtmg3); in mctl_init()
179 &mctl_ctl->dramtmg4); in mctl_init()
185 &mctl_ctl->dramtmg5); in mctl_init()
187 writel(0x00000008, &mctl_ctl->dramtmg8); in mctl_init()
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/external/u-boot/arch/arm/mach-sunxi/dram_timings/
Dddr3_1333.c7 struct sunxi_mctl_ctl_reg * const mctl_ctl = in mctl_set_timing_params() local
48 writel(0x1c70, &mctl_ctl->mr[0]); /* CL=11, WR=12 */ in mctl_set_timing_params()
49 writel(0x40, &mctl_ctl->mr[1]); in mctl_set_timing_params()
50 writel(0x18, &mctl_ctl->mr[2]); /* CWL=8 */ in mctl_set_timing_params()
51 writel(0x0, &mctl_ctl->mr[3]); in mctl_set_timing_params()
54 writel(0x3, &mctl_ctl->lp3mr11); /* odt_en[7:4] */ in mctl_set_timing_params()
59 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params()
61 &mctl_ctl->dramtmg[1]); in mctl_set_timing_params()
64 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params()
66 &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()
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Dddr2_v3s.c7 struct sunxi_mctl_ctl_reg * const mctl_ctl = in mctl_set_timing_params() local
48 writel(0x263, &mctl_ctl->mr[0]); in mctl_set_timing_params()
49 writel(0x4, &mctl_ctl->mr[1]); in mctl_set_timing_params()
50 writel(0x0, &mctl_ctl->mr[2]); in mctl_set_timing_params()
51 writel(0x0, &mctl_ctl->mr[3]); in mctl_set_timing_params()
56 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params()
58 &mctl_ctl->dramtmg[1]); in mctl_set_timing_params()
61 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params()
63 &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()
65 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
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Dlpddr3_stock.c7 struct sunxi_mctl_ctl_reg * const mctl_ctl = in mctl_set_timing_params() local
48 writel(0xc3, &mctl_ctl->mr[1]); /* nWR=8, BL8 */ in mctl_set_timing_params()
49 writel(0xa, &mctl_ctl->mr[2]); /* RL=12, WL=6 */ in mctl_set_timing_params()
50 writel(0x2, &mctl_ctl->mr[3]); /* 40 0hms PD/PU */ in mctl_set_timing_params()
55 &mctl_ctl->dramtmg[0]); in mctl_set_timing_params()
57 &mctl_ctl->dramtmg[1]); in mctl_set_timing_params()
60 &mctl_ctl->dramtmg[2]); in mctl_set_timing_params()
62 &mctl_ctl->dramtmg[3]); in mctl_set_timing_params()
64 DRAMTMG4_TRP(trp), &mctl_ctl->dramtmg[4]); in mctl_set_timing_params()
67 &mctl_ctl->dramtmg[5]); in mctl_set_timing_params()
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