Searched refs:pll_cfg0 (Results 1 – 1 of 1) sorted by relevance
20 u32 pll_cfg0, pll_cfg1, pllout; in decode_frac_pll() local27 pll_cfg0 = readl(&ana_pll->arm_pll_cfg0); in decode_frac_pll()41 if (pll_cfg0 & FRAC_PLL_PD_MASK) in decode_frac_pll()45 if ((pll_cfg0 & FRAC_PLL_CLKE_MASK) == 0) in decode_frac_pll()48 pll_refclk_sel = pll_cfg0 & FRAC_PLL_REFCLK_SEL_MASK; in decode_frac_pll()59 if (pll_cfg0 & FRAC_PLL_BYPASS_MASK) in decode_frac_pll()62 divr_val = (pll_cfg0 & FRAC_PLL_REFCLK_DIV_VAL_MASK) >> in decode_frac_pll()64 divq_val = pll_cfg0 & FRAC_PLL_OUTPUT_DIV_VAL_MASK; in decode_frac_pll()80 u32 pll_cfg0, pll_cfg1, pll_cfg2; in decode_sscg_pll() local98 pll_cfg0 = readl(&ana_pll->sys_pll1_cfg0); in decode_sscg_pll()[all …]