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Searched refs:pllcr0 (Results 1 – 14 of 14) sorted by relevance

/external/u-boot/board/freescale/b4860qds/
Db4860qds.c632 u32 fcap, dcbias, bcap, pllcr1, pllcr0; in check_pll_locks() local
637 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
645 setbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
663 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
671 setbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
697 clrbits_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
699 pllcr0 = (in_be32 in check_pll_locks()
700 (&srds_regs->bank[pll_num].pllcr0)| in check_pll_locks()
702 out_be32(&srds_regs->bank[pll_num].pllcr0, in check_pll_locks()
703 pllcr0); in check_pll_locks()
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/external/u-boot/arch/powerpc/cpu/mpc85xx/
Dfsl_corenet2_serdes.c231 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
275 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
276 out_be32(&srds_regs->bank[pll_num].pllcr0, in serdes_init()
302 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
303 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 | in serdes_init()
309 pll_cr0 = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
310 out_be32(&srds_regs->bank[pll_num].pllcr0, pll_cr0 & in serdes_init()
318 pll_status = in_be32(&srds_regs->bank[pll_num].pllcr0); in serdes_init()
Dfsl_corenet_serdes.c400 clrsetbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr0, in p4080_erratum_serdes8()
403 clrsetbits_be32(&regs->bank[FSL_SRDS_BANK_3].pllcr0, in p4080_erratum_serdes8()
679 setbits_be32(&srds_regs->bank[bank].pllcr0, in fsl_serdes_init()
/external/u-boot/board/freescale/t1040qds/
Dt1040qds.c226 u32 pllcr0 = srds_regs->bank[i].pllcr0; in misc_init_r() local
227 u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
/external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/
Dfsl_lsch2_serdes.c320 reg = in_be32(&serdes1_base->bank[i].pllcr0); in setup_serdes_volt()
339 reg = in_be32(&serdes2_base->bank[i].pllcr0); in setup_serdes_volt()
380 reg = in_be32(&serdes1_base->bank[i].pllcr0); in setup_serdes_volt()
391 reg = in_be32(&serdes2_base->bank[i].pllcr0); in setup_serdes_volt()
Dfsl_lsch3_serdes.c288 reg = in_le32(&serdes_base->bank[i].pllcr0); in do_pll_reset_done()
320 reg = in_le32(&serdes_base->bank[i].pllcr0); in do_pll_lock()
/external/u-boot/board/freescale/t4qds/
Dt4240qds.c643 u32 pllcr0, expected; in misc_init_r() local
667 pllcr0 = srds_regs->bank[0].pllcr0; in misc_init_r()
668 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
/external/u-boot/board/freescale/p2041rdb/
Dp2041rdb.c201 u32 expected = in_be32(&regs->bank[i].pllcr0); in misc_init_r()
/external/u-boot/board/freescale/corenet_ds/
Dcorenet_ds.c174 u32 expected = srds_regs->bank[i].pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; in misc_init_r()
/external/u-boot/board/keymile/kmp204x/
Dkmp204x.c187 u32 actual = in_be32(&regs->bank[i].pllcr0); in misc_init_r()
/external/u-boot/arch/arm/include/asm/arch-fsl-layerscape/
Dimmap_lsch3.h397 u32 pllcr0; /* PLL Control Register 0 */ member
Dimmap_lsch2.h550 u32 pllcr0; /* PLL Control Register 0 */ member
/external/u-boot/arch/arm/include/asm/arch-ls102xa/
Dimmap_ls102xa.h343 u32 pllcr0; /* PLL Control Register 0 */ member
/external/u-boot/arch/powerpc/include/asm/
Dimmap_85xx.h2542 u32 pllcr0; /* PLL Control Register 0 */ member
2626 u32 pllcr0; /* PLL Control Register 0 */ member