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Searched refs:postdiv1 (Results 1 – 11 of 11) sorted by relevance

/external/u-boot/drivers/clk/rockchip/
Dclk_rk3128.c32 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
46 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
49 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
61 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
79 u32 postdiv1, postdiv2 = 1; in pll_para_config() local
92 postdiv1 = DIV_ROUND_UP(VCO_MIN_HZ / 1000, freq_khz); in pll_para_config()
93 if (postdiv1 > max_postdiv1) { in pll_para_config()
94 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
95 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_para_config()
98 vco_khz = freq_khz * postdiv1 * postdiv2; in pll_para_config()
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Dclk_rk3399.c35 u32 postdiv1; member
47 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
295 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
299 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
322 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | in rkclk_set_pll()
337 u32 postdiv1, postdiv2 = 1; in pll_para_config() local
350 postdiv1 = DIV_ROUND_UP(VCO_MIN_KHZ, freq_khz); in pll_para_config()
351 if (postdiv1 > max_postdiv1) { in pll_para_config()
352 postdiv2 = DIV_ROUND_UP(postdiv1, max_postdiv1); in pll_para_config()
353 postdiv1 = DIV_ROUND_UP(postdiv1, postdiv2); in pll_para_config()
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Dclk_rk322x.c31 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
49 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
52 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
64 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
173 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
199 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
204 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
325 {.refdiv = 1, .fbdiv = 50, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
329 {.refdiv = 1, .fbdiv = 75, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
333 {.refdiv = 1, .fbdiv = 100, .postdiv1 = 3, .postdiv2 = 1}; in rk322x_ddr_set_clk()
Dclk_rk3036.c34 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
52 uint output_hz = vco_hz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
56 pll, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
66 (div->postdiv1 << PLL_POSTDIV1_SHIFT) | div->fbdiv); in rkclk_set_pll()
172 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
198 postdiv1 = (con & PLL_POSTDIV1_MASK) >> PLL_POSTDIV1_SHIFT; in rkclk_pll_get_rate()
203 return (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
Dclk_rv1108.c32 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};\
63 uint32_t refdiv, fbdiv, postdiv1, postdiv2; in rkclk_pll_get_rate() local
75 postdiv1 = (con1 & POSTDIV1_MASK) >> POSTDIV1_SHIFT; in rkclk_pll_get_rate()
78 freq = (24 * fbdiv / (refdiv * postdiv1 * postdiv2)) * 1000000; in rkclk_pll_get_rate()
Dclk_rk3328.c23 u32 postdiv1; member
35 .postdiv1 = _postdiv1, .postdiv2 = _postdiv2};
242 u32 output_khz = vco_khz / div->postdiv1 / div->postdiv2; in rkclk_set_pll()
246 pll_con, div->fbdiv, div->refdiv, div->postdiv1, in rkclk_set_pll()
265 (div->postdiv1 << PLL_POSTDIV1_SHIFT)); in rkclk_set_pll()
/external/u-boot/arch/arm/include/asm/arch-rockchip/
Dcru_rv1108.h52 u32 postdiv1; member
Dcru_rk3036.h63 u32 postdiv1; member
Dcru_rk3128.h66 u32 postdiv1; member
Dcru_rk322x.h64 u32 postdiv1; member
/external/u-boot/arch/arm/mach-rockchip/rk3036/
Dsdram_rk3036.c340 (dpll_init_cfg.postdiv1 << PLL_POSTDIV1_SHIFT) | in rkdclk_init()