| /external/mesa3d/src/gallium/drivers/r600/ |
| D | r600_pipe_common.h | 141 struct r600_resource { struct
179 struct r600_resource *immed_buffer; argument
184 struct r600_resource *staging;
208 struct r600_resource resource;
225 struct r600_resource *cmask_buffer;
274 struct r600_resource *cb_buffer_fmask; /* Used for FMASK relocations. R600 only */
275 struct r600_resource *cb_buffer_cmask; /* Used for CMASK relocations. R600 only */
435 struct r600_resource *buf_filled_size;
517 struct r600_resource *eop_bug_scratch;
644 struct r600_resource *resource,
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| D | r600_buffer_common.c | 48 struct r600_resource *resource, in r600_buffer_map_sync_with_rings()
105 struct r600_resource *res, in r600_init_resource_fields()
196 struct r600_resource *res) in r600_alloc_resource()
236 struct r600_resource *rbuffer = r600_resource(buf); in r600_buffer_destroy()
247 struct r600_resource *rbuffer) in r600_invalidate_buffer()
280 struct r600_resource *rdst = r600_resource(dst); in r600_replace_buffer_storage()
281 struct r600_resource *rsrc = r600_resource(src); in r600_replace_buffer_storage()
302 struct r600_resource *rbuffer = r600_resource(resource); in r600_invalidate_resource()
314 void *data, struct r600_resource *staging, in r600_buffer_get_transfer()
359 struct r600_resource *rbuffer = r600_resource(resource); in r600_buffer_transfer_map()
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| D | r600_query.h | 41 struct r600_resource;
153 struct r600_resource *);
156 struct r600_resource *buffer, uint64_t va);
159 struct r600_resource *buffer, uint64_t va);
168 struct r600_resource *buf;
279 struct r600_resource *buffer, uint64_t va);
281 struct r600_resource *buffer, uint64_t va);
285 struct r600_resource *buffer, uint64_t va);
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| D | evergreen_hw_context.c | 40 struct r600_resource *rdst = (struct r600_resource*)dst; in evergreen_dma_copy_buffer()
41 struct r600_resource *rsrc = (struct r600_resource*)src; in evergreen_dma_copy_buffer()
98 util_range_add(&r600_resource(dst)->valid_buffer_range, offset, in evergreen_cp_dma_clear_buffer()
101 offset += r600_resource(dst)->gpu_address; in evergreen_cp_dma_clear_buffer()
128 (struct r600_resource*)dst, RADEON_USAGE_WRITE, in evergreen_cp_dma_clear_buffer()
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| D | evergreen_compute_internal.h | 43 struct r600_resource *code_bo;
49 struct r600_resource *kernel_param;
56 struct r600_resource* r600_compute_buffer_alloc_vram(struct r600_screen *screen, unsigned size);
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| D | r600_hw_context.c | 323 ctx->trace_buf = (struct r600_resource*) in r600_begin_new_cs()
437 struct r600_resource *buf = NULL; in r600_emit_pfp_sync_me()
501 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset, in r600_cp_dma_copy_buffer()
504 dst_offset += r600_resource(dst)->gpu_address; in r600_cp_dma_copy_buffer()
505 src_offset += r600_resource(src)->gpu_address; in r600_cp_dma_copy_buffer()
533 src_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, (struct r600_resource*)src, in r600_cp_dma_copy_buffer()
535 dst_reloc = radeon_add_to_buffer_list(&rctx->b, &rctx->b.gfx, (struct r600_resource*)dst, in r600_cp_dma_copy_buffer()
577 struct r600_resource *rdst = (struct r600_resource*)dst; in r600_dma_copy_buffer()
578 struct r600_resource *rsrc = (struct r600_resource*)src; in r600_dma_copy_buffer()
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| D | compute_memory_pool.h | 52 struct r600_resource *real_buffer;
64 struct r600_resource *bo; /**< The pool buffer object resource */
132 struct r600_resource* data, int offset_in_chunk,
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| D | evergreen_compute.h | 37 struct r600_resource base;
45 struct r600_resource* r600_compute_buffer_alloc_vram(struct r600_screen *screen, unsigned size);
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| D | r600_streamout.c | 47 struct r600_resource *rbuffer = (struct r600_resource*)buffer; in r600_create_so_target()
196 uint64_t va = r600_resource(t[i]->b.buffer)->gpu_address; in r600_emit_streamout_begin()
206 r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer), in r600_emit_streamout_begin()
216 r600_emit_reloc(rctx, &rctx->gfx, r600_resource(t[i]->b.buffer), in r600_emit_streamout_begin()
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| D | r600_cs.h | 71 struct r600_resource *rbo, in radeon_add_to_buffer_list()
102 struct r600_resource *rbo, in radeon_add_to_buffer_list_check_mem()
117 struct r600_ring *ring, struct r600_resource *rbo, in r600_emit_reloc()
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| /external/mesa3d/src/gallium/drivers/radeon/ |
| D | r600_pipe_common.h | 136 struct r600_resource { struct
186 struct r600_resource *staging; argument
210 struct r600_resource resource;
219 struct r600_resource *cmask_buffer;
262 struct r600_resource *dcc_separate_buffer;
264 struct r600_resource *last_dcc_separate_buffer;
397 struct r600_resource *eop_bug_scratch;
532 struct r600_resource *resource,
535 struct r600_resource *res,
538 struct r600_resource *res);
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| D | r600_buffer_common.c | 46 struct r600_resource *resource, in si_buffer_map_sync_with_rings()
103 struct r600_resource *res, in si_init_resource_fields()
199 struct r600_resource *res) in si_alloc_resource()
240 struct r600_resource *rbuffer = r600_resource(buf); in r600_buffer_destroy()
250 struct r600_resource *rbuffer) in r600_invalidate_buffer()
283 struct r600_resource *rdst = r600_resource(dst); in si_replace_buffer_storage()
284 struct r600_resource *rsrc = r600_resource(src); in si_replace_buffer_storage()
307 struct r600_resource *rbuffer = r600_resource(resource); in si_invalidate_resource()
319 void *data, struct r600_resource *staging, in r600_buffer_get_transfer()
352 struct r600_resource *rbuffer = r600_resource(resource); in r600_buffer_transfer_map()
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| D | r600_query.h | 37 struct r600_resource;
153 struct r600_resource *);
156 struct r600_resource *buffer, uint64_t va);
159 struct r600_resource *buffer, uint64_t va);
168 struct r600_resource *buf;
196 struct r600_resource *workaround_buf;
283 struct r600_resource *buffer, uint64_t va);
285 struct r600_resource *buffer, uint64_t va);
289 struct r600_resource *buffer, uint64_t va);
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| D | r600_pipe_common.c | 48 struct r600_resource *buf, uint64_t va, in si_gfx_write_event_eop()
74 struct r600_resource *scratch = ctx->eop_bug_scratch; in si_gfx_write_event_eop()
98 struct r600_resource *scratch = ctx->eop_bug_scratch; in si_gfx_write_event_eop()
170 struct r600_resource *dst, struct r600_resource *src) in si_need_dma_space()
377 struct r600_resource *res = r600_resource(resource); in r600_resource_commit()
434 rctx->eop_bug_scratch = (struct r600_resource*) in si_common_context_init()
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| D | r600_cs.h | 69 struct r600_resource *rbo, in radeon_add_to_buffer_list()
100 struct r600_resource *rbo, in radeon_add_to_buffer_list_check_mem()
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| /external/mesa3d/src/gallium/drivers/radeonsi/ |
| D | si_pm4.h | 38 struct r600_resource *indirect_buffer;
51 struct r600_resource *bo[SI_PM4_MAX_BO];
62 struct r600_resource *bo,
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| D | si_descriptors.c | 202 si_get_sampler_view_priority(struct r600_resource *res) in si_get_sampler_view_priority()
241 struct r600_resource *rres; in si_sampler_view_add_buffer()
255 rres = (struct r600_resource*)resource; in si_sampler_view_add_buffer()
291 static void si_set_buf_desc_address(struct r600_resource *buf, in si_set_buf_desc_address()
668 struct r600_resource *res = (struct r600_resource *)view->resource; in si_mark_image_range_valid()
683 struct r600_resource *res; in si_set_shader_image_desc()
685 res = (struct r600_resource *)view->resource; in si_set_shader_image_desc()
771 struct r600_resource *res; in si_set_shader_image()
780 res = (struct r600_resource *)view->resource; in si_set_shader_image()
955 r600_resource(buffers->buffers[i]), in si_buffer_resources_begin_new_cs()
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| D | si_cp_dma.c | 179 (struct r600_resource*)dst, in si_cp_dma_prepare()
183 (struct r600_resource*)src, in si_cp_dma_prepare()
212 struct r600_resource *rdst = r600_resource(dst); in si_clear_buffer()
374 sctx->scratch_buffer = (struct r600_resource*) in si_cp_dma_realign_engine()
418 util_range_add(&r600_resource(dst)->valid_buffer_range, dst_offset, in si_copy_buffer()
422 dst_offset += r600_resource(dst)->gpu_address; in si_copy_buffer()
423 src_offset += r600_resource(src)->gpu_address; in si_copy_buffer()
490 r600_resource(dst)->TC_L2_dirty = true; in si_copy_buffer()
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| D | si_pipe.h | 335 struct r600_resource *buf_filled_size;
418 struct r600_resource *trace_buf;
443 struct r600_resource *wait_mem_scratch;
515 struct r600_resource *border_color_buffer;
565 struct r600_resource *scratch_buffer;
569 struct r600_resource *compute_scratch_buffer;
751 struct r600_resource *res = (struct r600_resource *)r; in si_context_add_resource_size()
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| D | si_compute.c | 269 va = r600_resource(resources[i])->gpu_address; in si_set_global_binding()
343 sctx->compute_scratch_buffer = (struct r600_resource*) in si_setup_compute_scratch_buffer()
545 struct r600_resource *dispatch_buf = NULL; in si_setup_user_sgprs_co_v2()
614 struct r600_resource *input_buffer = NULL; in si_upload_compute_input()
685 uint64_t base_va = r600_resource(info->indirect)->gpu_address; in si_setup_tgsi_grid()
690 (struct r600_resource *)info->indirect, in si_setup_tgsi_grid()
758 uint64_t base_va = r600_resource(info->indirect)->gpu_address; in si_emit_dispatch_packets()
761 (struct r600_resource *)info->indirect, in si_emit_dispatch_packets()
829 r600_resource(info->indirect)->TC_L2_dirty) { in si_launch_grid()
831 r600_resource(info->indirect)->TC_L2_dirty = false; in si_launch_grid()
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| D | si_state_streamout.c | 47 struct r600_resource *rbuffer = (struct r600_resource*)buffer; in si_create_so_target()
115 r600_resource(sctx->streamout.targets[i]->b.buffer)->TC_L2_dirty = true; in si_set_streamout_targets()
183 uint64_t va = r600_resource(buffer)->gpu_address; in si_set_streamout_targets()
205 (struct r600_resource*)buffer, in si_set_streamout_targets()
209 r600_resource(buffer)->bind_history |= PIPE_BIND_STREAM_OUTPUT; in si_set_streamout_targets()
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| D | si_dma.c | 38 struct r600_resource *rdst = (struct r600_resource*)dst; in si_dma_copy_buffer()
39 struct r600_resource *rsrc = (struct r600_resource*)src; in si_dma_copy_buffer()
87 struct r600_resource *rdst = r600_resource(dst); in si_dma_clear_buffer()
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| D | si_pm4.c | 88 struct r600_resource *bo, in si_pm4_add_bo()
136 struct r600_resource *ib = state->indirect_buffer; in si_pm4_emit()
170 state->indirect_buffer = (struct r600_resource*) in si_pm4_upload_indirect_buffer()
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| D | si_state_draw.c | 298 radeon_emit(cs, r600_resource(sctx->tess_offchip_ring)->gpu_address >> 16); in si_emit_derived_tess_state()
715 index_va = r600_resource(indexbuf)->gpu_address + index_offset; in si_emit_draw_packets()
718 (struct r600_resource *)indexbuf, in si_emit_draw_packets()
729 uint64_t indirect_va = r600_resource(indirect->buffer)->gpu_address; in si_emit_draw_packets()
741 (struct r600_resource *)indirect->buffer, in si_emit_draw_packets()
770 struct r600_resource *params_buf = in si_emit_draw_packets()
771 (struct r600_resource *)indirect->indirect_draw_count; in si_emit_draw_packets()
1373 r600_resource(indexbuf)->TC_L2_dirty) { in si_draw_vbo()
1377 r600_resource(indexbuf)->TC_L2_dirty = false; in si_draw_vbo()
1389 if (r600_resource(indirect->buffer)->TC_L2_dirty) { in si_draw_vbo()
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| D | cik_sdma.c | 37 struct r600_resource *rdst = r600_resource(dst); in cik_sdma_copy_buffer()
38 struct r600_resource *rsrc = r600_resource(src); in cik_sdma_copy_buffer()
78 struct r600_resource *rdst = r600_resource(dst); in cik_sdma_clear_buffer()
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