| /external/u-boot/drivers/rtc/ |
| D | s3c24x0_rtc.c | 34 writeb(readb(&rtc->rtccon) | 0x01, &rtc->rtccon); in SetRTC_Access()
38 writeb(readb(&rtc->rtccon) & ~0x01, &rtc->rtccon); in SetRTC_Access()
57 sec = readb(&rtc->bcdsec); in rtc_get()
58 min = readb(&rtc->bcdmin); in rtc_get()
59 hour = readb(&rtc->bcdhour); in rtc_get()
60 mday = readb(&rtc->bcddate); in rtc_get()
61 wday = readb(&rtc->bcdday); in rtc_get()
62 mon = readb(&rtc->bcdmon); in rtc_get()
63 year = readb(&rtc->bcdyear); in rtc_get()
64 } while (sec != readb(&rtc->bcdsec)); in rtc_get()
[all …]
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| /external/u-boot/drivers/serial/ |
| D | mcfuart.c | 102 while (!(readb(&uart->usr) & UART_USR_TXRDY)) in mcf_serial_putc()
113 while (!(readb(&uart->usr) & UART_USR_RXRDY)) in mcf_serial_getc()
116 return readb(&uart->urb); in mcf_serial_getc()
130 return readb(&uart->usr) & UART_USR_RXRDY; in mcf_serial_tstc()
172 if (!(readb(&uart->usr) & UART_USR_TXRDY)) in coldfire_serial_putc()
186 if (!(readb(&uart->usr) & UART_USR_RXRDY)) in coldfire_serial_getc()
189 return readb(&uart->urb); in coldfire_serial_getc()
208 return readb(&uart->usr) & UART_USR_RXRDY ? 1 : 0; in coldfire_serial_pending()
210 return readb(&uart->usr) & UART_USR_TXRDY ? 0 : 1; in coldfire_serial_pending()
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| D | serial_arc.c | 55 while (!(readb(®s->status) & UART_TXEMPTY)) in arc_serial_putc()
65 return !(readb(®s->status) & UART_RXEMPTY); in arc_serial_tstc()
72 uint32_t status = readb(®s->status); in arc_serial_pending()
89 if (readb(®s->status) & UART_OVERFLOW_ERR) in arc_serial_getc()
92 return readb(®s->data) & 0xFF; in arc_serial_getc()
150 while (!(readb(®s->status) & UART_TXEMPTY)) in _debug_uart_putc()
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| /external/u-boot/drivers/usb/musb/ |
| D | musb_udc.c | 112 b = readb(&musbr->faddr); in musb_db_regs()
115 b = readb(&musbr->power); in musb_db_regs()
121 b = readb(&musbr->devctl); in musb_db_regs()
124 b = readb(&musbr->ep[0].ep0.configdata); in musb_db_regs()
130 b = readb(&musbr->index); in musb_db_regs()
154 power = readb(&musbr->power); in musb_peri_softconnect()
159 readb(&musbr->intrusb); in musb_peri_softconnect()
166 power = readb(&musbr->power); in musb_peri_softconnect()
176 devctl = readb(&musbr->devctl); in musb_peri_softconnect()
260 faddr = readb(&musbr->faddr); in musb_peri_ep0_set_address()
[all …]
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| D | musb_hcd.c | 286 rxedlength = readb(&musbr->rxcount); in ctrlreq_in_data_phase()
432 u8 power = readb(&musbr->power); in musb_port_reset()
443 power = readb(&musbr->power); in musb_port_reset()
1016 if (readb(&musbr->devctl) & MUSB_DEVCTL_HM) in usb_lowlevel_init()
1024 power = readb(&musbr->power); in usb_lowlevel_init()
1031 power = readb(&musbr->power); in usb_lowlevel_init()
1036 musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ? in usb_lowlevel_init()
1038 ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ? in usb_lowlevel_init()
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| /external/u-boot/drivers/i2c/ |
| D | fsl_i2c.c | 230 while (!(readb(&base->sr) & I2C_SR_MBB)) { in fsl_i2c_fixup()
235 if (readb(&base->sr) & I2C_SR_MAL) { in fsl_i2c_fixup()
243 readb(&base->dr); in fsl_i2c_fixup()
246 while (!(readb(&base->sr) & I2C_SR_MIF)) { in fsl_i2c_fixup()
281 while (readb(&base->sr) & I2C_SR_MBB) { in __i2c_init()
298 while (readb(&base->sr) & I2C_SR_MBB) { in i2c_wait4bus()
313 csr = readb(&base->sr); in i2c_wait()
317 csr = readb(&base->sr); in i2c_wait()
382 readb(&base->dr); in __i2c_read_data()
398 data[i] = readb(&base->dr); in __i2c_read_data()
[all …]
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| D | mxc_i2c.c | 202 sr = readb(base + (I2SR << reg_shift)); in wait_for_sr_state()
211 __func__, sr, readb(base + (I2CR << reg_shift)), in wait_for_sr_state()
223 sr, readb(base + (I2CR << reg_shift)), state); in wait_for_sr_state()
263 unsigned int temp = readb(base + (I2CR << reg_shift)); in i2c_imx_stop()
290 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS; in i2c_init_transfer_()
292 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN); in i2c_init_transfer_()
300 if (readb(base + (IADR << reg_shift)) == (chip << 1)) in i2c_init_transfer_()
308 temp = readb(base + (I2CR << reg_shift)); in i2c_init_transfer_()
483 temp = readb(base + (I2CR << reg_shift)); in i2c_read_data()
490 readb(base + (I2DR << reg_shift)); in i2c_read_data()
[all …]
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| D | sh_i2c.c | 72 if (SH_IC_DTE & readb(&dev->icsr)) in sh_irq_dte()
83 if (SH_IC_DTE & readb(&dev->icsr)) in sh_irq_dte_with_tack()
85 if (SH_IC_TACK & readb(&dev->icsr)) in sh_irq_dte_with_tack()
97 if (!(SH_IC_BUSY & readb(&dev->icsr))) in sh_irq_busy()
192 ret = readb(&dev->icdr) & 0xff; in sh_i2c_raw_read()
195 readb(&dev->icdr); /* Dummy read */ in sh_i2c_raw_read()
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| D | rcar_iic.c | 52 if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR)) in sh_irq_dte()
64 if (RCAR_IC_DTE & readb(priv->base + RCAR_IIC_ICSR)) in sh_irq_dte_with_tack()
66 if (RCAR_IC_TACK & readb(priv->base + RCAR_IIC_ICSR)) in sh_irq_dte_with_tack()
79 if (!(RCAR_IC_BUSY & readb(priv->base + RCAR_IIC_ICSR))) in sh_irq_busy()
130 msg->buf[i] = readb(priv->base + RCAR_IIC_ICDR) & 0xff; in rcar_iic_read_common()
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| /external/u-boot/arch/sh/cpu/sh2/ |
| D | cpu.c | 14 writeb(readb(STBCR4) & ~0x04, STBCR4);\
17 writeb(readb(STBCR4) & ~0x80, STBCR4);\
20 writeb(readb(STBCR4) & ~0x10, STBCR4);\
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| /external/u-boot/board/astro/mcf5373l/ |
| D | mcf5373l.c | 150 if (readb(&uart->usr) & UART_USR_TXRDY) in astro_put_char()
163 return readb(&uart->usr) & UART_USR_RXRDY; in astro_is_char()
171 while (!(readb(&uart->usr) & UART_USR_RXRDY)) ; in astro_get_char()
172 return readb(&uart->urb); in astro_get_char()
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| D | fpga.c | 35 tmp_char = readb(&gpiop->par_timer); in altera_pre_fn()
81 if (readb(&gpiop->ppd_pwm) & 0x08) in altera_status_fn()
91 if (readb(&gpiop->ppd_pwm) & 0x20) in altera_done_fn()
223 return (readb(&gpiop->ppd_pwm) & 0x08) == 0; in xilinx_init_config_fn()
231 return (readb(&gpiop->ppd_pwm) & 0x20) >> 5; in xilinx_done_config_fn()
258 tmp_char = readb(&gpiop->par_timer); in xilinx_pre_config_fn()
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| /external/u-boot/board/renesas/sh7785lcr/ |
| D | selfcheck.c | 25 printf("PLD version = %04x\n", readb(PLD_VERSR)); in test_pld()
47 while (readb(PLD_SWSR) != 0x05) { in test_dipsw()
52 while (readb(PLD_SWSR) != 0x0A) { in test_dipsw()
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| /external/u-boot/drivers/gpio/ |
| D | hi6220_gpio.c | 18 data = readb(bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_input()
40 data = readb(bank->base + HI6220_GPIO_DIR); in hi6220_gpio_direction_output()
53 return !!readb(bank->base + (BIT(gpio + 2))); in hi6220_gpio_get_value()
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| /external/u-boot/arch/microblaze/include/asm/ |
| D | io.h | 23 #define readb(addr) \ macro
41 #define inb(addr) readb (addr)
49 #define in_8(addr) readb (addr)
67 #define __raw_readb readb
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| /external/u-boot/cmd/ |
| D | pcmcia.c | 333 …printf("Configuration Option Register: %02x @ %x\n", readb(addr + config_base), addr + config_base… in check_ide_device()
334 printf("Card Configuration and Status Register: %02x\n", readb(addr + config_base + 2)); in check_ide_device()
335 printf("Pin Replacement Register Register: %02x\n", readb(addr + config_base + 4)); in check_ide_device()
336 printf("Socket and Copy Register: %02x\n", readb(addr + config_base + 6)); in check_ide_device()
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| /external/u-boot/drivers/net/ |
| D | cs8900.c | 56 readb(iob); in get_reg_init_bus()
57 readb(iob + 1); in get_reg_init_bus()
58 readb(iob); in get_reg_init_bus()
59 readb(iob + 1); in get_reg_init_bus()
60 readb(iob); in get_reg_init_bus()
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| /external/u-boot/arch/arm/mach-omap2/omap3/ |
| D | spl_id_nand.c | 52 *mfr = readb(&gpmc_cfg->cs[0].nand_dat); in identify_nand_chip()
53 *id = readb(&gpmc_cfg->cs[0].nand_dat); in identify_nand_chip()
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| /external/u-boot/arch/sh/lib/ |
| D | time.c | 37 writeb(readb(&tmu->tstr) | (1 << timer), &tmu->tstr); in tmu_timer_start()
44 writeb(readb(&tmu->tstr) & ~(1 << timer), &tmu->tstr); in tmu_timer_stop()
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| /external/u-boot/arch/xtensa/include/asm/ |
| D | io.h | 35 #define readb(addr) \ macro
45 #define __raw_readb readb
59 #define inb(port) readb((u8 *)((port)))
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| /external/u-boot/drivers/mmc/ |
| D | tegra_mmc.c | 86 ctrl = readb(&priv->reg->hostctl); in tegra_mmc_prepare_data()
252 readb(offset - 1); in tegra_mmc_send_cmd_bounced()
423 ctrl = readb(&priv->reg->hostctl); in tegra_mmc_set_ios()
491 while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) { in tegra_mmc_reset()
503 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl)); in tegra_mmc_reset()
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| /external/u-boot/include/ |
| D | iotrace.h | 60 #undef readb
61 #define readb(addr) iotrace_readb((const void *)(uintptr_t)addr) macro
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| /external/u-boot/arch/arm/cpu/arm926ejs/mxs/ |
| D | clock.c | 62 clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_CPU]); in mxs_get_pclk()
105 clkfrac = readb(&clkctrl_regs->hw_clkctrl_frac0[CLKCTRL_FRAC0_EMI]); in mxs_get_emiclk()
135 clkfrac = readb(reg); in mxs_get_gpmiclk()
189 ret = readb(&clkctrl_regs->hw_clkctrl_frac0[io_reg]) & in mxs_get_ioclk()
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| /external/u-boot/board/renesas/sh7752evb/ |
| D | sh7752evb.c | 87 writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */ in init_gether_mdio()
167 writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */ in board_mmc_init()
169 writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */ in board_mmc_init()
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| /external/u-boot/arch/sh/include/asm/ |
| D | io.h | 146 #define readb(c) ({ unsigned int __v = __raw_readb(__mem_pci(c)); __v; }) macro
169 if (readb(io_addr) != *signature) in check_signature()
180 #elif !defined(readb)
182 #define readb(addr) __raw_readb(addr) macro
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