1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * (C) Copyright 2009 SAMSUNG Electronics
4 * Minkyu Kang <mk7.kang@samsung.com>
5 * Jaehoon Chung <jh80.chung@samsung.com>
6 * Portions Copyright 2011-2016 NVIDIA Corporation
7 */
8
9 #include <bouncebuf.h>
10 #include <common.h>
11 #include <dm.h>
12 #include <errno.h>
13 #include <mmc.h>
14 #include <asm/gpio.h>
15 #include <asm/io.h>
16 #include <asm/arch-tegra/tegra_mmc.h>
17
18 struct tegra_mmc_plat {
19 struct mmc_config cfg;
20 struct mmc mmc;
21 };
22
23 struct tegra_mmc_priv {
24 struct tegra_mmc *reg;
25 struct reset_ctl reset_ctl;
26 struct clk clk;
27 struct gpio_desc cd_gpio; /* Change Detect GPIO */
28 struct gpio_desc pwr_gpio; /* Power GPIO */
29 struct gpio_desc wp_gpio; /* Write Protect GPIO */
30 unsigned int version; /* SDHCI spec. version */
31 unsigned int clock; /* Current clock (MHz) */
32 };
33
tegra_mmc_set_power(struct tegra_mmc_priv * priv,unsigned short power)34 static void tegra_mmc_set_power(struct tegra_mmc_priv *priv,
35 unsigned short power)
36 {
37 u8 pwr = 0;
38 debug("%s: power = %x\n", __func__, power);
39
40 if (power != (unsigned short)-1) {
41 switch (1 << power) {
42 case MMC_VDD_165_195:
43 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8;
44 break;
45 case MMC_VDD_29_30:
46 case MMC_VDD_30_31:
47 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0;
48 break;
49 case MMC_VDD_32_33:
50 case MMC_VDD_33_34:
51 pwr = TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3;
52 break;
53 }
54 }
55 debug("%s: pwr = %X\n", __func__, pwr);
56
57 /* Set the bus voltage first (if any) */
58 writeb(pwr, &priv->reg->pwrcon);
59 if (pwr == 0)
60 return;
61
62 /* Now enable bus power */
63 pwr |= TEGRA_MMC_PWRCTL_SD_BUS_POWER;
64 writeb(pwr, &priv->reg->pwrcon);
65 }
66
tegra_mmc_prepare_data(struct tegra_mmc_priv * priv,struct mmc_data * data,struct bounce_buffer * bbstate)67 static void tegra_mmc_prepare_data(struct tegra_mmc_priv *priv,
68 struct mmc_data *data,
69 struct bounce_buffer *bbstate)
70 {
71 unsigned char ctrl;
72
73
74 debug("buf: %p (%p), data->blocks: %u, data->blocksize: %u\n",
75 bbstate->bounce_buffer, bbstate->user_buffer, data->blocks,
76 data->blocksize);
77
78 writel((u32)(unsigned long)bbstate->bounce_buffer, &priv->reg->sysad);
79 /*
80 * DMASEL[4:3]
81 * 00 = Selects SDMA
82 * 01 = Reserved
83 * 10 = Selects 32-bit Address ADMA2
84 * 11 = Selects 64-bit Address ADMA2
85 */
86 ctrl = readb(&priv->reg->hostctl);
87 ctrl &= ~TEGRA_MMC_HOSTCTL_DMASEL_MASK;
88 ctrl |= TEGRA_MMC_HOSTCTL_DMASEL_SDMA;
89 writeb(ctrl, &priv->reg->hostctl);
90
91 /* We do not handle DMA boundaries, so set it to max (512 KiB) */
92 writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize);
93 writew(data->blocks, &priv->reg->blkcnt);
94 }
95
tegra_mmc_set_transfer_mode(struct tegra_mmc_priv * priv,struct mmc_data * data)96 static void tegra_mmc_set_transfer_mode(struct tegra_mmc_priv *priv,
97 struct mmc_data *data)
98 {
99 unsigned short mode;
100 debug(" mmc_set_transfer_mode called\n");
101 /*
102 * TRNMOD
103 * MUL1SIN0[5] : Multi/Single Block Select
104 * RD1WT0[4] : Data Transfer Direction Select
105 * 1 = read
106 * 0 = write
107 * ENACMD12[2] : Auto CMD12 Enable
108 * ENBLKCNT[1] : Block Count Enable
109 * ENDMA[0] : DMA Enable
110 */
111 mode = (TEGRA_MMC_TRNMOD_DMA_ENABLE |
112 TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE);
113
114 if (data->blocks > 1)
115 mode |= TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT;
116
117 if (data->flags & MMC_DATA_READ)
118 mode |= TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ;
119
120 writew(mode, &priv->reg->trnmod);
121 }
122
tegra_mmc_wait_inhibit(struct tegra_mmc_priv * priv,struct mmc_cmd * cmd,struct mmc_data * data,unsigned int timeout)123 static int tegra_mmc_wait_inhibit(struct tegra_mmc_priv *priv,
124 struct mmc_cmd *cmd,
125 struct mmc_data *data,
126 unsigned int timeout)
127 {
128 /*
129 * PRNSTS
130 * CMDINHDAT[1] : Command Inhibit (DAT)
131 * CMDINHCMD[0] : Command Inhibit (CMD)
132 */
133 unsigned int mask = TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD;
134
135 /*
136 * We shouldn't wait for data inhibit for stop commands, even
137 * though they might use busy signaling
138 */
139 if ((data == NULL) && (cmd->resp_type & MMC_RSP_BUSY))
140 mask |= TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT;
141
142 while (readl(&priv->reg->prnsts) & mask) {
143 if (timeout == 0) {
144 printf("%s: timeout error\n", __func__);
145 return -1;
146 }
147 timeout--;
148 udelay(1000);
149 }
150
151 return 0;
152 }
153
tegra_mmc_send_cmd_bounced(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data,struct bounce_buffer * bbstate)154 static int tegra_mmc_send_cmd_bounced(struct udevice *dev, struct mmc_cmd *cmd,
155 struct mmc_data *data,
156 struct bounce_buffer *bbstate)
157 {
158 struct tegra_mmc_priv *priv = dev_get_priv(dev);
159 int flags, i;
160 int result;
161 unsigned int mask = 0;
162 unsigned int retry = 0x100000;
163 debug(" mmc_send_cmd called\n");
164
165 result = tegra_mmc_wait_inhibit(priv, cmd, data, 10 /* ms */);
166
167 if (result < 0)
168 return result;
169
170 if (data)
171 tegra_mmc_prepare_data(priv, data, bbstate);
172
173 debug("cmd->arg: %08x\n", cmd->cmdarg);
174 writel(cmd->cmdarg, &priv->reg->argument);
175
176 if (data)
177 tegra_mmc_set_transfer_mode(priv, data);
178
179 if ((cmd->resp_type & MMC_RSP_136) && (cmd->resp_type & MMC_RSP_BUSY))
180 return -1;
181
182 /*
183 * CMDREG
184 * CMDIDX[13:8] : Command index
185 * DATAPRNT[5] : Data Present Select
186 * ENCMDIDX[4] : Command Index Check Enable
187 * ENCMDCRC[3] : Command CRC Check Enable
188 * RSPTYP[1:0]
189 * 00 = No Response
190 * 01 = Length 136
191 * 10 = Length 48
192 * 11 = Length 48 Check busy after response
193 */
194 if (!(cmd->resp_type & MMC_RSP_PRESENT))
195 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE;
196 else if (cmd->resp_type & MMC_RSP_136)
197 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136;
198 else if (cmd->resp_type & MMC_RSP_BUSY)
199 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY;
200 else
201 flags = TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48;
202
203 if (cmd->resp_type & MMC_RSP_CRC)
204 flags |= TEGRA_MMC_TRNMOD_CMD_CRC_CHECK;
205 if (cmd->resp_type & MMC_RSP_OPCODE)
206 flags |= TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK;
207 if (data)
208 flags |= TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER;
209
210 debug("cmd: %d\n", cmd->cmdidx);
211
212 writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg);
213
214 for (i = 0; i < retry; i++) {
215 mask = readl(&priv->reg->norintsts);
216 /* Command Complete */
217 if (mask & TEGRA_MMC_NORINTSTS_CMD_COMPLETE) {
218 if (!data)
219 writel(mask, &priv->reg->norintsts);
220 break;
221 }
222 }
223
224 if (i == retry) {
225 printf("%s: waiting for status update\n", __func__);
226 writel(mask, &priv->reg->norintsts);
227 return -ETIMEDOUT;
228 }
229
230 if (mask & TEGRA_MMC_NORINTSTS_CMD_TIMEOUT) {
231 /* Timeout Error */
232 debug("timeout: %08x cmd %d\n", mask, cmd->cmdidx);
233 writel(mask, &priv->reg->norintsts);
234 return -ETIMEDOUT;
235 } else if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
236 /* Error Interrupt */
237 debug("error: %08x cmd %d\n", mask, cmd->cmdidx);
238 writel(mask, &priv->reg->norintsts);
239 return -1;
240 }
241
242 if (cmd->resp_type & MMC_RSP_PRESENT) {
243 if (cmd->resp_type & MMC_RSP_136) {
244 /* CRC is stripped so we need to do some shifting. */
245 for (i = 0; i < 4; i++) {
246 unsigned long offset = (unsigned long)
247 (&priv->reg->rspreg3 - i);
248 cmd->response[i] = readl(offset) << 8;
249
250 if (i != 3) {
251 cmd->response[i] |=
252 readb(offset - 1);
253 }
254 debug("cmd->resp[%d]: %08x\n",
255 i, cmd->response[i]);
256 }
257 } else if (cmd->resp_type & MMC_RSP_BUSY) {
258 for (i = 0; i < retry; i++) {
259 /* PRNTDATA[23:20] : DAT[3:0] Line Signal */
260 if (readl(&priv->reg->prnsts)
261 & (1 << 20)) /* DAT[0] */
262 break;
263 }
264
265 if (i == retry) {
266 printf("%s: card is still busy\n", __func__);
267 writel(mask, &priv->reg->norintsts);
268 return -ETIMEDOUT;
269 }
270
271 cmd->response[0] = readl(&priv->reg->rspreg0);
272 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
273 } else {
274 cmd->response[0] = readl(&priv->reg->rspreg0);
275 debug("cmd->resp[0]: %08x\n", cmd->response[0]);
276 }
277 }
278
279 if (data) {
280 unsigned long start = get_timer(0);
281
282 while (1) {
283 mask = readl(&priv->reg->norintsts);
284
285 if (mask & TEGRA_MMC_NORINTSTS_ERR_INTERRUPT) {
286 /* Error Interrupt */
287 writel(mask, &priv->reg->norintsts);
288 printf("%s: error during transfer: 0x%08x\n",
289 __func__, mask);
290 return -1;
291 } else if (mask & TEGRA_MMC_NORINTSTS_DMA_INTERRUPT) {
292 /*
293 * DMA Interrupt, restart the transfer where
294 * it was interrupted.
295 */
296 unsigned int address = readl(&priv->reg->sysad);
297
298 debug("DMA end\n");
299 writel(TEGRA_MMC_NORINTSTS_DMA_INTERRUPT,
300 &priv->reg->norintsts);
301 writel(address, &priv->reg->sysad);
302 } else if (mask & TEGRA_MMC_NORINTSTS_XFER_COMPLETE) {
303 /* Transfer Complete */
304 debug("r/w is done\n");
305 break;
306 } else if (get_timer(start) > 8000UL) {
307 writel(mask, &priv->reg->norintsts);
308 printf("%s: MMC Timeout\n"
309 " Interrupt status 0x%08x\n"
310 " Interrupt status enable 0x%08x\n"
311 " Interrupt signal enable 0x%08x\n"
312 " Present status 0x%08x\n",
313 __func__, mask,
314 readl(&priv->reg->norintstsen),
315 readl(&priv->reg->norintsigen),
316 readl(&priv->reg->prnsts));
317 return -1;
318 }
319 }
320 writel(mask, &priv->reg->norintsts);
321 }
322
323 udelay(1000);
324 return 0;
325 }
326
tegra_mmc_send_cmd(struct udevice * dev,struct mmc_cmd * cmd,struct mmc_data * data)327 static int tegra_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
328 struct mmc_data *data)
329 {
330 void *buf;
331 unsigned int bbflags;
332 size_t len;
333 struct bounce_buffer bbstate;
334 int ret;
335
336 if (data) {
337 if (data->flags & MMC_DATA_READ) {
338 buf = data->dest;
339 bbflags = GEN_BB_WRITE;
340 } else {
341 buf = (void *)data->src;
342 bbflags = GEN_BB_READ;
343 }
344 len = data->blocks * data->blocksize;
345
346 bounce_buffer_start(&bbstate, buf, len, bbflags);
347 }
348
349 ret = tegra_mmc_send_cmd_bounced(dev, cmd, data, &bbstate);
350
351 if (data)
352 bounce_buffer_stop(&bbstate);
353
354 return ret;
355 }
356
tegra_mmc_change_clock(struct tegra_mmc_priv * priv,uint clock)357 static void tegra_mmc_change_clock(struct tegra_mmc_priv *priv, uint clock)
358 {
359 ulong rate;
360 int div;
361 unsigned short clk;
362 unsigned long timeout;
363
364 debug(" mmc_change_clock called\n");
365
366 /*
367 * Change Tegra SDMMCx clock divisor here. Source is PLLP_OUT0
368 */
369 if (clock == 0)
370 goto out;
371
372 rate = clk_set_rate(&priv->clk, clock);
373 div = (rate + clock - 1) / clock;
374 debug("div = %d\n", div);
375
376 writew(0, &priv->reg->clkcon);
377
378 /*
379 * CLKCON
380 * SELFREQ[15:8] : base clock divided by value
381 * ENSDCLK[2] : SD Clock Enable
382 * STBLINTCLK[1] : Internal Clock Stable
383 * ENINTCLK[0] : Internal Clock Enable
384 */
385 div >>= 1;
386 clk = ((div << TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT) |
387 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE);
388 writew(clk, &priv->reg->clkcon);
389
390 /* Wait max 10 ms */
391 timeout = 10;
392 while (!(readw(&priv->reg->clkcon) &
393 TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE)) {
394 if (timeout == 0) {
395 printf("%s: timeout error\n", __func__);
396 return;
397 }
398 timeout--;
399 udelay(1000);
400 }
401
402 clk |= TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE;
403 writew(clk, &priv->reg->clkcon);
404
405 debug("mmc_change_clock: clkcon = %08X\n", clk);
406
407 out:
408 priv->clock = clock;
409 }
410
tegra_mmc_set_ios(struct udevice * dev)411 static int tegra_mmc_set_ios(struct udevice *dev)
412 {
413 struct tegra_mmc_priv *priv = dev_get_priv(dev);
414 struct mmc *mmc = mmc_get_mmc_dev(dev);
415 unsigned char ctrl;
416 debug(" mmc_set_ios called\n");
417
418 debug("bus_width: %x, clock: %d\n", mmc->bus_width, mmc->clock);
419
420 /* Change clock first */
421 tegra_mmc_change_clock(priv, mmc->clock);
422
423 ctrl = readb(&priv->reg->hostctl);
424
425 /*
426 * WIDE8[5]
427 * 0 = Depend on WIDE4
428 * 1 = 8-bit mode
429 * WIDE4[1]
430 * 1 = 4-bit mode
431 * 0 = 1-bit mode
432 */
433 if (mmc->bus_width == 8)
434 ctrl |= (1 << 5);
435 else if (mmc->bus_width == 4)
436 ctrl |= (1 << 1);
437 else
438 ctrl &= ~(1 << 1 | 1 << 5);
439
440 writeb(ctrl, &priv->reg->hostctl);
441 debug("mmc_set_ios: hostctl = %08X\n", ctrl);
442
443 return 0;
444 }
445
tegra_mmc_pad_init(struct tegra_mmc_priv * priv)446 static void tegra_mmc_pad_init(struct tegra_mmc_priv *priv)
447 {
448 #if defined(CONFIG_TEGRA30)
449 u32 val;
450
451 debug("%s: sdmmc address = %08x\n", __func__, (unsigned int)priv->reg);
452
453 /* Set the pad drive strength for SDMMC1 or 3 only */
454 if (priv->reg != (void *)0x78000000 &&
455 priv->reg != (void *)0x78000400) {
456 debug("%s: settings are only valid for SDMMC1/SDMMC3!\n",
457 __func__);
458 return;
459 }
460
461 val = readl(&priv->reg->sdmemcmppadctl);
462 val &= 0xFFFFFFF0;
463 val |= MEMCOMP_PADCTRL_VREF;
464 writel(val, &priv->reg->sdmemcmppadctl);
465
466 val = readl(&priv->reg->autocalcfg);
467 val &= 0xFFFF0000;
468 val |= AUTO_CAL_PU_OFFSET | AUTO_CAL_PD_OFFSET | AUTO_CAL_ENABLED;
469 writel(val, &priv->reg->autocalcfg);
470 #endif
471 }
472
tegra_mmc_reset(struct tegra_mmc_priv * priv,struct mmc * mmc)473 static void tegra_mmc_reset(struct tegra_mmc_priv *priv, struct mmc *mmc)
474 {
475 unsigned int timeout;
476 debug(" mmc_reset called\n");
477
478 /*
479 * RSTALL[0] : Software reset for all
480 * 1 = reset
481 * 0 = work
482 */
483 writeb(TEGRA_MMC_SWRST_SW_RESET_FOR_ALL, &priv->reg->swrst);
484
485 priv->clock = 0;
486
487 /* Wait max 100 ms */
488 timeout = 100;
489
490 /* hw clears the bit when it's done */
491 while (readb(&priv->reg->swrst) & TEGRA_MMC_SWRST_SW_RESET_FOR_ALL) {
492 if (timeout == 0) {
493 printf("%s: timeout error\n", __func__);
494 return;
495 }
496 timeout--;
497 udelay(1000);
498 }
499
500 /* Set SD bus voltage & enable bus power */
501 tegra_mmc_set_power(priv, fls(mmc->cfg->voltages) - 1);
502 debug("%s: power control = %02X, host control = %02X\n", __func__,
503 readb(&priv->reg->pwrcon), readb(&priv->reg->hostctl));
504
505 /* Make sure SDIO pads are set up */
506 tegra_mmc_pad_init(priv);
507 }
508
tegra_mmc_init(struct udevice * dev)509 static int tegra_mmc_init(struct udevice *dev)
510 {
511 struct tegra_mmc_priv *priv = dev_get_priv(dev);
512 struct mmc *mmc = mmc_get_mmc_dev(dev);
513 unsigned int mask;
514 debug(" tegra_mmc_init called\n");
515
516 tegra_mmc_reset(priv, mmc);
517
518 #if defined(CONFIG_TEGRA124_MMC_DISABLE_EXT_LOOPBACK)
519 /*
520 * Disable the external clock loopback and use the internal one on
521 * SDMMC3 as per the SDMMC_VENDOR_MISC_CNTRL_0 register's SDMMC_SPARE1
522 * bits being set to 0xfffd according to the TRM.
523 *
524 * TODO(marcel.ziswiler@toradex.com): Move to device tree controlled
525 * approach once proper kernel integration made it mainline.
526 */
527 if (priv->reg == (void *)0x700b0400) {
528 mask = readl(&priv->reg->venmiscctl);
529 mask &= ~TEGRA_MMC_MISCON_ENABLE_EXT_LOOPBACK;
530 writel(mask, &priv->reg->venmiscctl);
531 }
532 #endif
533
534 priv->version = readw(&priv->reg->hcver);
535 debug("host version = %x\n", priv->version);
536
537 /* mask all */
538 writel(0xffffffff, &priv->reg->norintstsen);
539 writel(0xffffffff, &priv->reg->norintsigen);
540
541 writeb(0xe, &priv->reg->timeoutcon); /* TMCLK * 2^27 */
542 /*
543 * NORMAL Interrupt Status Enable Register init
544 * [5] ENSTABUFRDRDY : Buffer Read Ready Status Enable
545 * [4] ENSTABUFWTRDY : Buffer write Ready Status Enable
546 * [3] ENSTADMAINT : DMA boundary interrupt
547 * [1] ENSTASTANSCMPLT : Transfre Complete Status Enable
548 * [0] ENSTACMDCMPLT : Command Complete Status Enable
549 */
550 mask = readl(&priv->reg->norintstsen);
551 mask &= ~(0xffff);
552 mask |= (TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE |
553 TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE |
554 TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT |
555 TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY |
556 TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY);
557 writel(mask, &priv->reg->norintstsen);
558
559 /*
560 * NORMAL Interrupt Signal Enable Register init
561 * [1] ENSTACMDCMPLT : Transfer Complete Signal Enable
562 */
563 mask = readl(&priv->reg->norintsigen);
564 mask &= ~(0xffff);
565 mask |= TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE;
566 writel(mask, &priv->reg->norintsigen);
567
568 return 0;
569 }
570
tegra_mmc_getcd(struct udevice * dev)571 static int tegra_mmc_getcd(struct udevice *dev)
572 {
573 struct tegra_mmc_priv *priv = dev_get_priv(dev);
574
575 debug("tegra_mmc_getcd called\n");
576
577 if (dm_gpio_is_valid(&priv->cd_gpio))
578 return dm_gpio_get_value(&priv->cd_gpio);
579
580 return 1;
581 }
582
583 static const struct dm_mmc_ops tegra_mmc_ops = {
584 .send_cmd = tegra_mmc_send_cmd,
585 .set_ios = tegra_mmc_set_ios,
586 .get_cd = tegra_mmc_getcd,
587 };
588
tegra_mmc_probe(struct udevice * dev)589 static int tegra_mmc_probe(struct udevice *dev)
590 {
591 struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
592 struct tegra_mmc_plat *plat = dev_get_platdata(dev);
593 struct tegra_mmc_priv *priv = dev_get_priv(dev);
594 struct mmc_config *cfg = &plat->cfg;
595 int bus_width, ret;
596
597 cfg->name = dev->name;
598
599 bus_width = dev_read_u32_default(dev, "bus-width", 1);
600
601 cfg->voltages = MMC_VDD_32_33 | MMC_VDD_33_34 | MMC_VDD_165_195;
602 cfg->host_caps = 0;
603 if (bus_width == 8)
604 cfg->host_caps |= MMC_MODE_8BIT;
605 if (bus_width >= 4)
606 cfg->host_caps |= MMC_MODE_4BIT;
607 cfg->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
608
609 /*
610 * min freq is for card identification, and is the highest
611 * low-speed SDIO card frequency (actually 400KHz)
612 * max freq is highest HS eMMC clock as per the SD/MMC spec
613 * (actually 52MHz)
614 */
615 cfg->f_min = 375000;
616 cfg->f_max = 48000000;
617
618 cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
619
620 priv->reg = (void *)dev_read_addr(dev);
621
622 ret = reset_get_by_name(dev, "sdhci", &priv->reset_ctl);
623 if (ret) {
624 debug("reset_get_by_name() failed: %d\n", ret);
625 return ret;
626 }
627 ret = clk_get_by_index(dev, 0, &priv->clk);
628 if (ret) {
629 debug("clk_get_by_index() failed: %d\n", ret);
630 return ret;
631 }
632
633 ret = reset_assert(&priv->reset_ctl);
634 if (ret)
635 return ret;
636 ret = clk_enable(&priv->clk);
637 if (ret)
638 return ret;
639 ret = clk_set_rate(&priv->clk, 20000000);
640 if (IS_ERR_VALUE(ret))
641 return ret;
642 ret = reset_deassert(&priv->reset_ctl);
643 if (ret)
644 return ret;
645
646 /* These GPIOs are optional */
647 gpio_request_by_name(dev, "cd-gpios", 0, &priv->cd_gpio, GPIOD_IS_IN);
648 gpio_request_by_name(dev, "wp-gpios", 0, &priv->wp_gpio, GPIOD_IS_IN);
649 gpio_request_by_name(dev, "power-gpios", 0, &priv->pwr_gpio,
650 GPIOD_IS_OUT);
651 if (dm_gpio_is_valid(&priv->pwr_gpio))
652 dm_gpio_set_value(&priv->pwr_gpio, 1);
653
654 upriv->mmc = &plat->mmc;
655
656 return tegra_mmc_init(dev);
657 }
658
tegra_mmc_bind(struct udevice * dev)659 static int tegra_mmc_bind(struct udevice *dev)
660 {
661 struct tegra_mmc_plat *plat = dev_get_platdata(dev);
662
663 return mmc_bind(dev, &plat->mmc, &plat->cfg);
664 }
665
666 static const struct udevice_id tegra_mmc_ids[] = {
667 { .compatible = "nvidia,tegra20-sdhci" },
668 { .compatible = "nvidia,tegra30-sdhci" },
669 { .compatible = "nvidia,tegra114-sdhci" },
670 { .compatible = "nvidia,tegra124-sdhci" },
671 { .compatible = "nvidia,tegra210-sdhci" },
672 { .compatible = "nvidia,tegra186-sdhci" },
673 { }
674 };
675
676 U_BOOT_DRIVER(tegra_mmc_drv) = {
677 .name = "tegra_mmc",
678 .id = UCLASS_MMC,
679 .of_match = tegra_mmc_ids,
680 .bind = tegra_mmc_bind,
681 .probe = tegra_mmc_probe,
682 .ops = &tegra_mmc_ops,
683 .platdata_auto_alloc_size = sizeof(struct tegra_mmc_plat),
684 .priv_auto_alloc_size = sizeof(struct tegra_mmc_priv),
685 };
686