| /external/e2fsprogs/lib/ss/ |
| D | request_tbl.c | 55 register ssrt **rt1, **rt2; in ss_delete_request_table() local
60 for (rt2 = rt1; *rt1; rt1++) { in ss_delete_request_table()
62 *rt2++ = *rt1; in ss_delete_request_table()
66 *rt2 = (ssrt *)NULL; in ss_delete_request_table()
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| /external/tensorflow/tensorflow/python/ops/ragged/ |
| D | ragged_tensor_bounding_shape_op_test.py | 40 rt2 = ragged_tensor.RaggedTensor.from_row_splits(values, [0, 7])
43 self.assertRaggedEqual(rt2.bounding_shape(), [1, 7])
49 rt2 = ragged_tensor.RaggedTensor.from_row_splits(values, [0, 7])
52 self.assertRaggedEqual(rt2.bounding_shape(), [1, 7, 2])
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| D | ragged_range_op_test.py | 36 rt2 = ragged_math_ops.range([0, 5, 8], [3, 3, 12])
37 self.assertRaggedEqual(rt2, [[0, 1, 2], [], [8, 9, 10, 11]])
99 rt2 = ragged_math_ops.range([0, 5, 5], [0, 3, 5], -1)
101 self.assertRaggedEqual(rt2, [[], [5, 4], []])
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| D | ragged_tensor_test.py | 134 rt2 = RaggedTensor.from_row_lengths(values, row_lengths=[4, 0, 3, 1, 0])
139 for rt in (rt1, rt2, rt3, rt4, rt5):
141 del rt1, rt2, rt3, rt4, rt5
606 rt2 = RaggedTensor.from_value_rowids(values, value_rowids)
608 for rt in [rt1, rt2]:
629 rt2 = RaggedTensor.from_value_rowids(values, value_rowids)
631 for rt in [rt1, rt2]:
664 rt2 = RaggedTensor.from_nested_value_rowids(values, nested_value_rowids)
666 for rt in [rt1, rt2]:
696 rt2 = RaggedTensor.from_row_splits(
[all …]
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| D | ragged_to_sparse_op_test.py | 187 rt2 = ragged_factory_ops.constant(
189 rt = ragged_functional_ops.map_flat_values(math_ops.add, rt1, rt2 * 2.0)
193 [rt1.flat_values, rt2.flat_values])
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Verifier/ |
| D | recursive-type-3.ll | 3 %rt2 = type { i32, { i8, %rt2*, i8 }, i32 }
9 %0 = alloca %rt2
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| D | recursive-type-1.ll | 3 %rt2 = type { i32, { i8, %rt2, i8 }, i32 }
10 %0 = alloca %rt2
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| D | recursive-type-2.ll | 3 %rt1 = type { i32, { i8, %rt2, i8 }, i32 }
4 %rt2 = type { i64, { i6, %rt3 } }
12 %0 = alloca %rt2
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| /external/llvm/test/Verifier/ |
| D | recursive-type-3.ll | 3 %rt2 = type { i32, { i8, %rt2*, i8 }, i32 }
9 %0 = alloca %rt2
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| D | recursive-type-1.ll | 3 %rt2 = type { i32, { i8, %rt2, i8 }, i32 }
10 %0 = alloca %rt2
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| D | recursive-type-2.ll | 3 %rt1 = type { i32, { i8, %rt2, i8 }, i32 }
4 %rt2 = type { i64, { i6, %rt3 } }
12 %0 = alloca %rt2
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | returnaddr.ll | 11 define i8* @rt2() nounwind readnone {
13 ; CHECK-LABEL: rt2:
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| D | arm64-returnaddr.ll | 12 define i8* @rt2() nounwind readnone {
14 ; CHECK-LABEL: rt2:
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| /external/llvm/test/CodeGen/AArch64/ |
| D | returnaddr.ll | 11 define i8* @rt2() nounwind readnone {
13 ; CHECK-LABEL: rt2:
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| D | arm64-returnaddr.ll | 12 define i8* @rt2() nounwind readnone {
14 ; CHECK-LABEL: rt2:
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| /external/swiftshader/third_party/LLVM/test/CodeGen/ARM/ |
| D | arm-returnaddr.ll | 17 define i8* @rt2() nounwind readnone {
19 ; CHECK: rt2:
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| /external/llvm/test/CodeGen/ARM/ |
| D | arm-returnaddr.ll | 16 define i8* @rt2() nounwind readnone {
18 ; CHECK-LABEL: rt2:
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/ARM/ |
| D | arm-returnaddr.ll | 16 define i8* @rt2() nounwind readnone {
18 ; CHECK-LABEL: rt2:
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| /external/vixl/src/aarch32/ |
| D | macro-assembler-aarch32.cc | 1677 Register rt2, in Delegate() argument
1686 temps.Include(rt, rt2); in Delegate()
1689 ldrd(rt, rt2, MemOperandComputationHelper(cond, scratch, location, mask)); in Delegate()
1693 Assembler::Delegate(type, instruction, cond, rt, rt2, location); in Delegate()
1898 Register rt2, in Delegate() argument
1919 if (((rt.GetCode() + 1) % kNumberOfRegisters) != rt2.GetCode()) { in Delegate()
1950 if (!rt2.Is(rn)) temps.Include(rt2); in Delegate()
1965 rt2, in Delegate()
1975 if (!rt2.Is(rn)) temps.Include(rt2); in Delegate()
1990 rt2, in Delegate()
[all …]
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| /external/vixl/src/aarch64/ |
| D | simulator-aarch64.cc | 1549 unsigned rt2 = instr->GetRt2(); in LoadStorePairHelper() local
1559 VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || (rt != rt2)); in LoadStorePairHelper()
1566 WriteWRegister(rt2, Memory::Read<uint32_t>(address2), NoRegLog); in LoadStorePairHelper()
1571 WriteSRegister(rt2, Memory::Read<float>(address2), NoRegLog); in LoadStorePairHelper()
1576 WriteXRegister(rt2, Memory::Read<uint64_t>(address2), NoRegLog); in LoadStorePairHelper()
1581 WriteDRegister(rt2, Memory::Read<double>(address2), NoRegLog); in LoadStorePairHelper()
1586 WriteQRegister(rt2, Memory::Read<qreg_t>(address2), NoRegLog); in LoadStorePairHelper()
1591 WriteXRegister(rt2, Memory::Read<int32_t>(address2), NoRegLog); in LoadStorePairHelper()
1596 Memory::Write<uint32_t>(address2, ReadWRegister(rt2)); in LoadStorePairHelper()
1601 Memory::Write<float>(address2, ReadSRegister(rt2)); in LoadStorePairHelper()
[all …]
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| D | assembler-aarch64.cc | 1078 const CPURegister& rt2, in ldp() argument
1080 LoadStorePair(rt, rt2, src, LoadPairOpFor(rt, rt2)); in ldp()
1085 const CPURegister& rt2, in stp() argument
1087 LoadStorePair(rt, rt2, dst, StorePairOpFor(rt, rt2)); in stp()
1100 const CPURegister& rt2, in LoadStorePair() argument
1103 VIXL_ASSERT(CPUHas(rt, rt2)); in LoadStorePair()
1106 VIXL_ASSERT(((op & LoadStorePairLBit) == 0) || !rt.Is(rt2)); in LoadStorePair()
1107 VIXL_ASSERT(AreSameSizeAndType(rt, rt2)); in LoadStorePair()
1111 Instr memop = op | Rt(rt) | Rt2(rt2) | RnSP(addr.GetBaseRegister()) | in LoadStorePair()
1130 const CPURegister& rt2, in ldnp() argument
[all …]
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| D | assembler-aarch64.h | 1285 const CPURegister& rt2,
1290 const CPURegister& rt2,
1298 const CPURegister& rt2,
1303 const CPURegister& rt2,
1339 const Register& rt2,
1343 void ldxp(const Register& rt, const Register& rt2, const MemOperand& src);
1366 const Register& rt2,
1370 void ldaxp(const Register& rt, const Register& rt2, const MemOperand& src);
1448 const Register& rt2,
1455 const Register& rt2,
[all …]
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| D | macro-assembler-aarch64.h | 62 V(Ldp, CPURegister&, rt, rt2, LoadPairOpFor(rt, rt2)) \
63 V(Stp, CPURegister&, rt, rt2, StorePairOpFor(rt, rt2)) \
64 V(Ldpsw, CPURegister&, rt, rt2, LDPSW_x)
784 const CPURegister& rt2,
1641 void Ldaxp(const Register& rt, const Register& rt2, const MemOperand& src) { in Ldaxp() argument
1643 VIXL_ASSERT(!rt.Aliases(rt2)); in Ldaxp()
1645 ldaxp(rt, rt2, src); in Ldaxp()
1701 const Register& rt2, \
1705 ASM(rs, rs2, rt, rt2, src); \
1796 const CPURegister& rt2, in Ldnp() argument
[all …]
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| /external/v8/src/arm64/ |
| D | simulator-arm64.cc | 1859 unsigned rt2 = instr->Rt2(); in LoadStorePairHelper() local
1896 DCHECK(((op & LoadStorePairLBit) == 0) || (rt != rt2)); in LoadStorePairHelper()
1904 set_wreg_no_log(rt2, MemoryRead<uint32_t>(address2)); in LoadStorePairHelper()
1910 set_sreg_no_log(rt2, MemoryRead<float>(address2)); in LoadStorePairHelper()
1916 set_xreg_no_log(rt2, MemoryRead<uint64_t>(address2)); in LoadStorePairHelper()
1922 set_dreg_no_log(rt2, MemoryRead<double>(address2)); in LoadStorePairHelper()
1928 set_qreg(rt2, MemoryRead<qreg_t>(address2), NoRegLog); in LoadStorePairHelper()
1934 set_xreg_no_log(rt2, MemoryRead<int32_t>(address2)); in LoadStorePairHelper()
1940 MemoryWrite<uint32_t>(address2, wreg(rt2)); in LoadStorePairHelper()
1946 MemoryWrite<float>(address2, sreg(rt2)); in LoadStorePairHelper()
[all …]
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| /external/pdfium/xfa/fxfa/ |
| D | cxfa_ffpageview.cpp | 424 const CFX_RectF& rt2 = arg2->GetWidget()->GetWidgetRect(); in OrderContainer() local
425 if (rt1.top - rt2.top >= XFA_FLOAT_PERCISION) in OrderContainer()
426 return rt1.top < rt2.top; in OrderContainer()
427 return rt1.left < rt2.left; in OrderContainer()
|