/external/clang/test/CodeGen/ |
D | BasicInstrs.c | 19 _Bool setlt(int X, int Y) { in setlt() function
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/external/swiftshader/third_party/LLVM/lib/Target/Mips/ |
D | Mips64InstrInfo.td | 100 def SLTi64 : SetCC_I<0x0a, "slti", setlt, simm16_64, immSExt16, CPU64Regs>; 108 def SLT64 : SetCC_R<0x00, 0x2a, "slt", setlt, CPU64Regs>; 163 def BLTZ64 : CBranchZero<0x01, 0, "bltz", setlt, CPU64Regs>;
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/external/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrFloat.td | 67 def : Pat<(setlt f32:$lhs, f32:$rhs), (LT_F32 f32:$lhs, f32:$rhs)>; 73 def : Pat<(setlt f64:$lhs, f64:$rhs), (LT_F64 f64:$lhs, f64:$rhs)>;
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/external/llvm/test/Transforms/InstCombine/ |
D | setcc-strength-reduce.ll | 2 ; working. Basically this boils down to converting setlt,gt,le,ge instructions
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/InstCombine/ |
D | setcc-strength-reduce.ll | 2 ; working. Basically this boils down to converting setlt,gt,le,ge instructions
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/external/swiftshader/third_party/LLVM/test/Transforms/InstCombine/ |
D | setcc-strength-reduce.ll | 2 ; working. Basically this boils down to converting setlt,gt,le,ge instructions
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/external/swiftshader/third_party/llvm-7.0/llvm/test/Transforms/LoopStrengthReduce/ |
D | dont-hoist-simple-loop-constants.ll | 4 ; The setlt wants to use a value that is incremented one more than the dominant
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/external/llvm/test/Transforms/LoopStrengthReduce/ |
D | dont-hoist-simple-loop-constants.ll | 4 ; The setlt wants to use a value that is incremented one more than the dominant
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/external/swiftshader/third_party/LLVM/test/Transforms/LoopStrengthReduce/ |
D | dont-hoist-simple-loop-constants.ll | 4 ; The setlt wants to use a value that is incremented one more than the dominant
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/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/PowerPC/ |
D | ppc-vaarg-agg.ll | 44 ; with an error like: Cannot select: ch = setlt [ID=6]
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/external/llvm/test/CodeGen/PowerPC/ |
D | ppc-vaarg-agg.ll | 44 ; with an error like: Cannot select: ch = setlt [ID=6]
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/external/llvm/lib/Target/Hexagon/ |
D | HexagonInstrInfoVector.td | 306 def: InvertCmp_pat<A4_vcmpbgt, setlt, V8I8, i1>; 307 def: InvertCmp_pat<A4_vcmpbgt, setlt, V8I8, v8i1>; 308 def: InvertCmp_pat<A2_vcmphgt, setlt, V4I16, i1>; 309 def: InvertCmp_pat<A2_vcmphgt, setlt, V4I16, v4i1>; 310 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, i1>; 311 def: InvertCmp_pat<A2_vcmpwgt, setlt, V2I32, v2i1>;
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D | HexagonSelectCCInfo.td | 111 // setlt-64 -> setgt-64.
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D | HexagonInstrInfoV5.td | 494 def: Pat<(i1 (setlt F32:$src1, F32:$src2)), 496 def: Pat<(i1 (setlt F32:$src1, fpimm:$src2)), 498 def: Pat<(i1 (setlt F64:$src1, F64:$src2)), 500 def: Pat<(i1 (setlt F64:$src1, fpimm:$src2)),
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D | HexagonInstrInfoV3.td | 148 defm: MinMax_pats_p<setlt, A2_minp, A2_maxp>;
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/ |
D | WebAssemblyInstrFloat.td | 67 def : Pat<(setlt f32:$lhs, f32:$rhs), (LT_F32 f32:$lhs, f32:$rhs)>; 73 def : Pat<(setlt f64:$lhs, f64:$rhs), (LT_F64 f64:$lhs, f64:$rhs)>;
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/external/swiftshader/third_party/LLVM/lib/Target/CellSPU/ |
D | SPU64InstrInfo.td | 225 // i64 setge/setlt: 253 def : I64SETCCNegCond<setlt, I64GEr64>; 254 def : I64SELECTNegCond<setlt, I64GEr64>;
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/external/llvm/lib/Target/Mips/ |
D | Mips16InstrInfo.td | 1447 // bcond-setgt (do we need to have this pair of setlt, setgt??) 1470 // bcond-setlt 1473 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1478 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1631 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1767 // x > (k - 1) and then reverses the operands to use setlt. So this pattern 1801 // setlt 1803 def: SetCC_R16<setlt, SltCCRxRy16>; 1805 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
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D | Mips64InstrInfo.td | 104 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 130 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>; 241 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>; 543 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Mips/ |
D | Mips16InstrInfo.td | 1445 // bcond-setgt (do we need to have this pair of setlt, setgt??) 1468 // bcond-setlt 1471 <(brcond (i32 (setlt CPU16Regs:$rx, CPU16Regs:$ry)), bb:$imm16), 1476 <(brcond (i32 (setlt CPU16Regs:$rx, immSExt16:$imm)), bb:$imm16), 1629 (select (i32 (setlt CPU16Regs:$a, immSExt16:$b)), 1765 // x > (k - 1) and then reverses the operands to use setlt. So this pattern 1799 // setlt 1801 def: SetCC_R16<setlt, SltCCRxRy16>; 1803 def: SetCC_I16<setlt, immSExt16, SltiCCRxImmX16>;
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D | Mips64InstrInfo.td | 119 def SLTi64 : SetCC_I<"slti", setlt, simm16_64, immSExt16, GPR64Opnd>, 145 def SLT64 : SetCC_R<"slt", setlt, GPR64Opnd>, ADD_FM<0, 0x2a>, GPR_64; 267 def BLTZ64 : CBranchZero<"bltz", brtarget, setlt, GPR64Opnd>, BGEZ_FM<1, 0>, 711 def : MipsPat<(brcond (i32 (setlt i64:$lhs, 1)), bb:$dst),
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/external/swiftshader/third_party/LLVM/lib/Target/Alpha/ |
D | AlphaInstrInfo.td | 201 defm CMOVLT : cmov_inst<0x44, "cmovlt", CmpOpFrag<(setlt node:$R, 0)>>; 221 def : Pat<(select (setlt GPRC:$RCOND, 0), GPRC:$RTRUE, immUExt8:$RFALSE), 359 [(set GPRC:$RC, (setlt GPRC:$RA, GPRC:$RB))], s_iadd>; 361 [(set GPRC:$RC, (setlt GPRC:$RA, immUExt8:$L))], s_iadd>; 664 // [(set F8RC:$RC, (setlt F8RC:$RA, F8RC:$RB))]>; 750 def : Pat<(select (setlt F8RC:$RA, F8RC:$RB), F8RC:$st, F8RC:$sf), 793 def : Pat<(select (setlt F8RC:$RA, F8RC:$RB), F4RC:$st, F4RC:$sf), 915 def : Pat<(brcond (setlt GPRC:$RA, 0), bb:$DISP), 938 def : Pat<(brcond (setlt F8RC:$RA, immFPZ), bb:$DISP), 949 def : Pat<(brcond (setlt F8RC:$RA, F8RC:$RB), bb:$DISP),
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/external/clang/www/demo/ |
D | index.cgi | 99 …$input =~ s@\b(add|sub|mul|div|rem|and|or|xor|setne|seteq|setlt|setgt|setle|setge|phi|tail|call|ca…
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
D | HexagonPatterns.td | 533 def: Pat<(i1 (setlt I32:$Rs, s32_0ImmPred:$s10)), 538 // Patfrag to convert the usual comparison patfrags (e.g. setlt) to ones 547 def: OpR_RR_pat<C2_cmpgt, RevCmp<setlt>, i1, I32>; 552 def: OpR_RR_pat<C2_cmpgtp, RevCmp<setlt>, i1, I64>; 556 def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, i1, V8I8>; 557 def: OpR_RR_pat<A4_vcmpbgt, RevCmp<setlt>, v8i1, V8I8>; 566 def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, i1, V4I16>; 567 def: OpR_RR_pat<A2_vcmphgt, RevCmp<setlt>, v4i1, V4I16>; 576 def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, i1, V2I32>; 577 def: OpR_RR_pat<A2_vcmpwgt, RevCmp<setlt>, v2i1, V2I32>; [all …]
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/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/RISCV/ |
D | RISCVInstrInfo.td | 610 def : PatGprGpr<setlt, SLT>; 611 def : PatGprSimm12<setlt, SLTI>; 646 def : BccPat<setlt, BLT>;
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