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Searched refs:suq (Results 1 – 22 of 22) sorted by relevance

/external/llvm/test/CodeGen/NVPTX/
Dtexsurf-queries.ll11 declare i32 @llvm.nvvm.suq.width(i64)
12 declare i32 @llvm.nvvm.suq.height(i64)
61 ; SM20: suq.width.b32
62 ; SM30: suq.width.b32
63 %width = tail call i32 @llvm.nvvm.suq.width(i64 %surfHandle)
72 ; SM20: suq.width.b32 %r{{[0-9]+}}, [surf0]
73 ; SM30: suq.width.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
74 %width = tail call i32 @llvm.nvvm.suq.width(i64 %surfHandle)
82 ; SM20: suq.height.b32
83 ; SM30: suq.height.b32
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/NVPTX/
Dtexsurf-queries.ll11 declare i32 @llvm.nvvm.suq.width(i64)
12 declare i32 @llvm.nvvm.suq.height(i64)
61 ; SM20: suq.width.b32
62 ; SM30: suq.width.b32
63 %width = tail call i32 @llvm.nvvm.suq.width(i64 %surfHandle)
72 ; SM20: suq.width.b32 %r{{[0-9]+}}, [surf0]
73 ; SM30: suq.width.b32 %r{{[0-9]+}}, [%rd[[HANDLE:[0-9]+]]]
74 %width = tail call i32 @llvm.nvvm.suq.width(i64 %surfHandle)
82 ; SM20: suq.height.b32
83 ; SM30: suq.height.b32
[all …]
/external/mesa3d/src/gallium/drivers/nouveau/codegen/
Dnv50_ir_lowering_nvc0.cpp1787 NVC0LoweringPass::handleSUQ(TexInstruction *suq) in handleSUQ() argument
1789 int mask = suq->tex.mask; in handleSUQ()
1790 int dim = suq->tex.target.getDim(); in handleSUQ()
1791 int arg = dim + (suq->tex.target.isArray() || suq->tex.target.isCube()); in handleSUQ()
1792 Value *ind = suq->getIndirectR(); in handleSUQ()
1793 int slot = suq->tex.r; in handleSUQ()
1802 if (c == 1 && suq->tex.target == TEX_TARGET_1D_ARRAY) { in handleSUQ()
1807 bld.mkMov(suq->getDef(d++), loadSuInfo32(ind, slot, offset, suq->tex.bindless)); in handleSUQ()
1808 if (c == 2 && suq->tex.target.isCube()) in handleSUQ()
1809 bld.mkOp2(OP_DIV, TYPE_U32, suq->getDef(d - 1), suq->getDef(d - 1), in handleSUQ()
[all …]
/external/llvm/include/llvm/IR/
DIntrinsicsNVVM.td2529 "llvm.nvvm.suq.channel.order">,
2533 "llvm.nvvm.suq.channel.data.type">,
2537 "llvm.nvvm.suq.width">,
2541 "llvm.nvvm.suq.height">,
2545 "llvm.nvvm.suq.depth">,
2549 "llvm.nvvm.suq.array.size">,
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/IR/
DIntrinsicsNVVM.td2555 "llvm.nvvm.suq.channel.order">,
2559 "llvm.nvvm.suq.channel.data.type">,
2563 "llvm.nvvm.suq.width">,
2567 "llvm.nvvm.suq.height">,
2571 "llvm.nvvm.suq.depth">,
2575 "llvm.nvvm.suq.array.size">,
/external/tensorflow/tensorflow/examples/udacity/
D6_lstm.ipynb876 "s fiction of the feelly constive suq flanch earlied curauking bjoventation agent\n",
/external/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td4330 "suq.channel_order.b32 \t$d, [$a];",
4334 "suq.channel_data_type.b32 \t$d, [$a];",
4338 "suq.width.b32 \t$d, [$a];",
4342 "suq.height.b32 \t$d, [$a];",
4346 "suq.depth.b32 \t$d, [$a];",
4350 "suq.array_size.b32 \t$d, [$a];",
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/NVPTX/
DNVPTXIntrinsics.td4648 "suq.channel_order.b32 \t$d, [$a];",
4652 "suq.channel_data_type.b32 \t$d, [$a];",
4656 "suq.width.b32 \t$d, [$a];",
4660 "suq.height.b32 \t$d, [$a];",
4664 "suq.depth.b32 \t$d, [$a];",
4668 "suq.array_size.b32 \t$d, [$a];",
/external/swiftshader/third_party/llvm-7.0/configs/common/include/llvm/IR/
DIntrinsicEnums.inc4144 nvvm_suq_array_size, // llvm.nvvm.suq.array.size
4145 nvvm_suq_channel_data_type, // llvm.nvvm.suq.channel.data.type
4146 nvvm_suq_channel_order, // llvm.nvvm.suq.channel.order
4147 nvvm_suq_depth, // llvm.nvvm.suq.depth
4148 nvvm_suq_height, // llvm.nvvm.suq.height
4149 nvvm_suq_width, // llvm.nvvm.suq.width
DIntrinsicImpl.inc4170 "llvm.nvvm.suq.array.size",
4171 "llvm.nvvm.suq.channel.data.type",
4172 "llvm.nvvm.suq.channel.order",
4173 "llvm.nvvm.suq.depth",
4174 "llvm.nvvm.suq.height",
4175 "llvm.nvvm.suq.width",
13048 1, // llvm.nvvm.suq.array.size
13049 1, // llvm.nvvm.suq.channel.data.type
13050 1, // llvm.nvvm.suq.channel.order
13051 1, // llvm.nvvm.suq.depth
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Fuchsia/include/llvm/IR/
DIntrinsics.gen3383 nvvm_suq_array_size, // llvm.nvvm.suq.array.size
3384 nvvm_suq_channel_data_type, // llvm.nvvm.suq.channel.data.type
3385 nvvm_suq_channel_order, // llvm.nvvm.suq.channel.order
3386 nvvm_suq_depth, // llvm.nvvm.suq.depth
3387 nvvm_suq_height, // llvm.nvvm.suq.height
3388 nvvm_suq_width, // llvm.nvvm.suq.width
9441 "llvm.nvvm.suq.array.size",
9442 "llvm.nvvm.suq.channel.data.type",
9443 "llvm.nvvm.suq.channel.order",
9444 "llvm.nvvm.suq.depth",
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Windows/include/llvm/IR/
DIntrinsics.gen3383 nvvm_suq_array_size, // llvm.nvvm.suq.array.size
3384 nvvm_suq_channel_data_type, // llvm.nvvm.suq.channel.data.type
3385 nvvm_suq_channel_order, // llvm.nvvm.suq.channel.order
3386 nvvm_suq_depth, // llvm.nvvm.suq.depth
3387 nvvm_suq_height, // llvm.nvvm.suq.height
3388 nvvm_suq_width, // llvm.nvvm.suq.width
9441 "llvm.nvvm.suq.array.size",
9442 "llvm.nvvm.suq.channel.data.type",
9443 "llvm.nvvm.suq.channel.order",
9444 "llvm.nvvm.suq.depth",
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Linux/include/llvm/IR/
DIntrinsics.gen3383 nvvm_suq_array_size, // llvm.nvvm.suq.array.size
3384 nvvm_suq_channel_data_type, // llvm.nvvm.suq.channel.data.type
3385 nvvm_suq_channel_order, // llvm.nvvm.suq.channel.order
3386 nvvm_suq_depth, // llvm.nvvm.suq.depth
3387 nvvm_suq_height, // llvm.nvvm.suq.height
3388 nvvm_suq_width, // llvm.nvvm.suq.width
9441 "llvm.nvvm.suq.array.size",
9442 "llvm.nvvm.suq.channel.data.type",
9443 "llvm.nvvm.suq.channel.order",
9444 "llvm.nvvm.suq.depth",
[all …]
/external/swiftshader/third_party/llvm-subzero/build/MacOS/include/llvm/IR/
DIntrinsics.gen3377 nvvm_suq_array_size, // llvm.nvvm.suq.array.size
3378 nvvm_suq_channel_data_type, // llvm.nvvm.suq.channel.data.type
3379 nvvm_suq_channel_order, // llvm.nvvm.suq.channel.order
3380 nvvm_suq_depth, // llvm.nvvm.suq.depth
3381 nvvm_suq_height, // llvm.nvvm.suq.height
3382 nvvm_suq_width, // llvm.nvvm.suq.width
9401 "llvm.nvvm.suq.array.size",
9402 "llvm.nvvm.suq.channel.data.type",
9403 "llvm.nvvm.suq.channel.order",
9404 "llvm.nvvm.suq.depth",
[all …]
/external/swiftshader/third_party/llvm-subzero/build/Android/include/llvm/IR/
DIntrinsics.gen3383 nvvm_suq_array_size, // llvm.nvvm.suq.array.size
3384 nvvm_suq_channel_data_type, // llvm.nvvm.suq.channel.data.type
3385 nvvm_suq_channel_order, // llvm.nvvm.suq.channel.order
3386 nvvm_suq_depth, // llvm.nvvm.suq.depth
3387 nvvm_suq_height, // llvm.nvvm.suq.height
3388 nvvm_suq_width, // llvm.nvvm.suq.width
9441 "llvm.nvvm.suq.array.size",
9442 "llvm.nvvm.suq.channel.data.type",
9443 "llvm.nvvm.suq.channel.order",
9444 "llvm.nvvm.suq.depth",
[all …]
/external/cldr/tools/java/org/unicode/cldr/util/data/
Diso-639-3_Name_Index.tab6347 suq Suri Suri
Diso-639-3.tab6098 suq I L Suri
Dlanguage-subtag-registry32904 Subtag: suq
/external/icu/icu4c/source/data/misc/
DsupplementalData.txt6545 "suq~t",
/external/webrtc/talk/media/testdata/
Dh264-svc-99-640x360.rtpdump7631 !,�-���o�b�&F�%�,�N�*�j�!�S5̮'��&_��Z~����^��v,��,2��7����!��iĨF��`�%��>��8]�;�+��\�suq���…
/external/cldr/tools/java/org/unicode/cldr/util/data/transforms/
Dinternal_raw_IPA-old.txt190186 suq suk
Dinternal_raw_IPA.txt159186 suq %33653 suk