| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/ |
| D | swp-phi.ll | 63 %v49 = phi float [ undef, %b0 ], [ %v48, %b1 ]
82 %v68 = fmul float %v49, %v49
85 %v71 = fmul float %v49, %v48
87 %v73 = fmul float %v49, %v47
89 %v75 = fmul float %v49, %v46
91 %v77 = fmul float %v49, %v45
93 %v79 = fmul float %v49, %v44
95 %v81 = fmul float %v49, %v43
97 %v83 = fmul float %v49, %v42
99 %v85 = fmul float %v49, %v41
[all …]
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| D | early-if-merge-loop.ll | 19 %v7 = phi i32 [ 0, %b2 ], [ %v49, %should_merge ]
61 %v49 = trunc i64 %v48 to i32
74 %v58 = tail call i64 @llvm.hexagon.A2.combinew(i32 %v49, i32 %v30)
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| D | swp-bad-sched.ll | 33 %v5 = phi i32 [ %v49, %b3 ], [ 0, %b2 ]
85 %v49 = add nsw i32 %v5, 4
86 %v50 = icmp slt i32 %v49, %v2
93 %v51 = phi i32 [ 0, %b1 ], [ %v49, %b4 ]
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| D | sdr-reg-profit.ll | 33 %v9 = phi i32 [ %v6, %b2 ], [ %v49, %b8 ]
73 %v49 = load i32, i32* %v44, align 4
83 %v57 = zext i32 %v49 to i64
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| D | reg-scav-imp-use-dbl-vec.ll | 142 %v49 = phi i32 [ %v124, %b11 ], [ 0, %b10 ]
144 %v51 = add i32 %v49, %v33
149 %v56 = add i32 %v49, %v32
154 %v61 = add i32 %v31, %v49
159 %v66 = add i32 %v49, %v30
195 %v102 = shl nsw i32 %v49, 6
199 %v105 = or i32 %v49, 1
219 %v124 = add nuw nsw i32 %v49, 2
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| D | swp-disable-Os.ll | 63 %v49 = add i32 %v44, %v48
64 %v50 = add i32 %v45, %v49
68 %v54 = add i32 %v49, %v53
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| D | swp-sigma.ll | 119 %v48 = phi <16 x i32> [ %v49, %b6 ], [ %v8, %b5 ]
120 %v49 = phi <16 x i32> [ %v52, %b6 ], [ %v29, %b5 ]
126 %v55 = tail call <16 x i32> @llvm.hexagon.V6.vabsdiffub(<16 x i32> %v49, <16 x i32> %v47) #2
132 …1 = tail call <16 x i32> @llvm.hexagon.V6.vmux(<512 x i1> %v57, <16 x i32> %v8, <16 x i32> %v49) #2
136 %v65 = tail call <16 x i32> @llvm.hexagon.V6.vlalignbi(<16 x i32> %v49, <16 x i32> %v48, i32 1) #2
148 %v77 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v52, <16 x i32> %v49, i32 1) #2
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| D | bug-allocframe-size.ll | 98 %v49 = phi float* [ %v2, %b10 ], [ %v0, %b0 ]
99 %v50 = load float, float* %v49, align 4
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| D | swp-phi-chains.ll | 93 %v49 = ashr exact i32 %v48, 16
94 %v50 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v47, i32 %v43, i32 %v49)
97 %v52 = tail call i32 @llvm.hexagon.M2.mpy.acc.sat.ll.s1(i32 %v51, i32 %v40, i32 %v49)
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| D | v6vect-no-sideeffects.ll | 79 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v34, <16 x i32> %v45)
83 … call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v52, <16 x i32> %v49, <16 x i32> %v49)
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| D | vect_setcc_v2i16.ll | 88 %v49 = load <4 x i16>, <4 x i16>* %v48, align 8
90 store <4 x i16> %v49, <4 x i16>* %v50, align 8
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| D | expand-condsets.ll | 27 %v7 = phi i32* [ %a1, %b1 ], [ %v49, %b7 ]
75 %v49 = getelementptr i32, i32* %v7, i32 64
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| D | bkfir.ll | 71 %v49 = ashr i32 %v38, 18
72 %v50 = trunc i32 %v49 to i16
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| D | reg-scavengebug-5.ll | 67 %v49 = phi <16 x i32>* [ %v112, %b2 ], [ %v36, %b1 ]
75 %v57 = getelementptr inbounds <16 x i32>, <16 x i32>* %v49, i32 1
76 %v58 = load <16 x i32>, <16 x i32>* %v49, align 64
102 %v82 = getelementptr inbounds <16 x i32>, <16 x i32>* %v49, i32 2
122 %v100 = getelementptr inbounds <16 x i32>, <16 x i32>* %v49, i32 3
136 %v112 = getelementptr inbounds <16 x i32>, <16 x i32>* %v49, i32 4
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| D | v6-inlasm1.ll | 78 %v49 = call <16 x i32> @llvm.hexagon.V6.vrdelta(<16 x i32> %v47, <16 x i32> %v48)
79 store <16 x i32> %v49, <16 x i32>* %v15, align 64
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| D | reg_seq.ll | 65 %v49 = getelementptr inbounds i16, i16* %a3, i32 %v47
66 %v50 = load i16, i16* %v49, align 2, !tbaa !3
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| D | swp-phi-dep1.ll | 71 %v49 = zext i8 %v37 to i32
76 %v54 = sub i32 %v49, %v52
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| D | regscav-wrong-super-sub-regs.ll | 115 %v49 = load i32, i32* @g5, align 4, !tbaa !0
116 %v50 = icmp slt i32 %v13, %v49
142 %v68 = sub i32 %v49, %v5
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| D | v60-haar-postinc.ll | 74 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %v43, <16 x i32> %v45)
76 %v51 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v49, <16 x i32> %v48)
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| D | regalloc-block-overlap.ll | 132 %v49 = tail call <32 x i32> @llvm.hexagon.V6.lo.128B(<64 x i32> %v48)
133 %v50 = tail call <32 x i32> @llvm.hexagon.V6.vmpyiewuh.128B(<32 x i32> undef, <32 x i32> %v49) #2
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| D | swp-resmii-1.ll | 72 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vnavgh(<16 x i32> %v43, <16 x i32> %v45)
74 %v51 = tail call <16 x i32> @llvm.hexagon.V6.vsathub(<16 x i32> %v49, <16 x i32> %v48)
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| D | swp-epilog-phi5.ll | 106 %v49 = mul i32 %v43, 2
143 %v78 = add i32 %v49, -2
145 %v80 = add i32 %v49, -4
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| D | multi-cycle.ll | 65 %v49 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v45, <16 x i32> %v45)
67 %v51 = tail call <16 x i32> @llvm.hexagon.V6.vaddh(<16 x i32> %v48, <16 x i32> %v49)
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| D | swp-conv3x3-nested.ll | 99 %v49 = phi <16 x i32> [ %v31, %b3 ], [ %v57, %b4 ]
113 %v63 = tail call <16 x i32> @llvm.hexagon.V6.valignbi(<16 x i32> %v57, <16 x i32> %v49, i32 4) #2
117 %v67 = tail call <32 x i32> @llvm.hexagon.V6.vcombine(<16 x i32> %v63, <16 x i32> %v49) #2
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/ |
| D | float-cost.ll | 70 %v49 = fmul float %v48, 0x3FD99999A0000000
71 %v50 = fadd float %v49, %v44
|