1; RUN: llc -march=hexagon -enable-pipeliner=false < %s | FileCheck %s
2
3; Test that the vsplat and vmemu are not all serialized due to chain edges
4; caused by the hasSideEffects flag. The exact code generation may change
5; due to the scheduling changes, but we shouldn't see a series of
6; vsplat and vmemu instructions that each occur in a single packet.
7
8; CHECK: loop0(.LBB0_[[LOOP:.]],
9; CHECK: .LBB0_[[LOOP]]:
10; CHECK: vsplat
11; CHECK-NEXT: vsplat
12; CHECK: vsplat
13; CHECK-NEXT: vsplat
14; CHECK: endloop0
15
16@g0 = global [256 x i8] c"^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^00226644,,..**8888::66,,,,&&^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^22000022..4444>>::8888**..^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^<<66220000226644<<>>::^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^>><<446622000022>>", align 64
17
18; Function Attrs: nounwind
19define void @f0(i16** noalias nocapture readonly %a0, i16* noalias nocapture readonly %a1, i32* noalias nocapture %a2, i32 %a3, i32 %a4, i32 %a5, i32 %a6) #0 {
20b0:
21  %v0 = load <16 x i32>, <16 x i32>* bitcast ([256 x i8]* @g0 to <16 x i32>*), align 64, !tbaa !0
22  %v1 = load <16 x i32>, <16 x i32>* bitcast (i8* getelementptr inbounds ([256 x i8], [256 x i8]* @g0, i32 0, i32 64) to <16 x i32>*), align 64, !tbaa !0
23  %v2 = load <16 x i32>, <16 x i32>* bitcast (i8* getelementptr inbounds ([256 x i8], [256 x i8]* @g0, i32 0, i32 128) to <16 x i32>*), align 64, !tbaa !0
24  %v3 = load <16 x i32>, <16 x i32>* bitcast (i8* getelementptr inbounds ([256 x i8], [256 x i8]* @g0, i32 0, i32 192) to <16 x i32>*), align 64, !tbaa !0
25  %v4 = icmp sgt i32 %a5, 0
26  br i1 %v4, label %b1, label %b5
27
28b1:                                               ; preds = %b0
29  %v5 = bitcast i32* %a2 to <16 x i32>*
30  %v6 = tail call <16 x i32> @llvm.hexagon.V6.vd0()
31  %v7 = bitcast i16* %a1 to i64*
32  %v8 = mul nsw i32 %a3, 4
33  %v9 = add i32 %v8, %a6
34  %v10 = add i32 %v9, 32
35  %v11 = add i32 %a5, -1
36  br label %b2
37
38b2:                                               ; preds = %b4, %b1
39  %v12 = phi i32 [ 0, %b1 ], [ %v59, %b4 ]
40  %v13 = phi <16 x i32>* [ %v5, %b1 ], [ %v58, %b4 ]
41  %v14 = getelementptr i16*, i16** %a0, i32 %v12
42  br label %b3
43
44b3:                                               ; preds = %b3, %b2
45  %v15 = phi i16** [ %v14, %b2 ], [ %v57, %b3 ]
46  %v16 = phi i32 [ 0, %b2 ], [ %v55, %b3 ]
47  %v17 = phi i64* [ %v7, %b2 ], [ %v23, %b3 ]
48  %v18 = phi <16 x i32> [ %v6, %b2 ], [ %v54, %b3 ]
49  %v19 = load i16*, i16** %v15, align 4, !tbaa !3
50  %v20 = getelementptr inbounds i16, i16* %v19, i32 %v9
51  %v21 = getelementptr inbounds i64, i64* %v17, i32 1
52  %v22 = load i64, i64* %v17, align 8, !tbaa !0
53  %v23 = getelementptr inbounds i64, i64* %v17, i32 2
54  %v24 = load i64, i64* %v21, align 8, !tbaa !0
55  %v25 = trunc i64 %v22 to i32
56  %v26 = lshr i64 %v22, 32
57  %v27 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v25)
58  %v28 = trunc i64 %v26 to i32
59  %v29 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v28)
60  %v30 = trunc i64 %v24 to i32
61  %v31 = lshr i64 %v24, 32
62  %v32 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v30)
63  %v33 = trunc i64 %v31 to i32
64  %v34 = tail call <16 x i32> @llvm.hexagon.V6.lvsplatw(i32 %v33)
65  %v35 = bitcast i16* %v20 to <16 x i32>*
66  %v36 = load <16 x i32>, <16 x i32>* %v35, align 4, !tbaa !0
67  %v37 = getelementptr inbounds i16, i16* %v19, i32 %v10
68  %v38 = bitcast i16* %v37 to <16 x i32>*
69  %v39 = load <16 x i32>, <16 x i32>* %v38, align 4, !tbaa !0
70  %v40 = tail call <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32> %v39, <16 x i32> %v36)
71  %v41 = tail call <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32> %v40, <16 x i32> %v40)
72  %v42 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v0)
73  %v43 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v1)
74  %v44 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v2)
75  %v45 = tail call <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32> %v41, <16 x i32> %v3)
76  %v46 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v27, <16 x i32> %v42)
77  %v47 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v29, <16 x i32> %v43)
78  %v48 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v32, <16 x i32> %v44)
79  %v49 = tail call <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32> %v34, <16 x i32> %v45)
80  %v50 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32> %v46, <16 x i32> %v46)
81  %v51 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v50, <16 x i32> %v47, <16 x i32> %v47)
82  %v52 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v51, <16 x i32> %v48, <16 x i32> %v48)
83  %v53 = tail call <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32> %v52, <16 x i32> %v49, <16 x i32> %v49)
84  %v54 = tail call <16 x i32> @llvm.hexagon.V6.vasrw.acc(<16 x i32> %v18, <16 x i32> %v53, i32 6)
85  %v55 = add nsw i32 %v16, 1
86  %v56 = icmp eq i32 %v16, 7
87  %v57 = getelementptr i16*, i16** %v15, i32 1
88  br i1 %v56, label %b4, label %b3
89
90b4:                                               ; preds = %b3
91  %v58 = getelementptr inbounds <16 x i32>, <16 x i32>* %v13, i32 1
92  store <16 x i32> %v54, <16 x i32>* %v13, align 64, !tbaa !0
93  %v59 = add nsw i32 %v12, 1
94  %v60 = icmp eq i32 %v12, %v11
95  br i1 %v60, label %b5, label %b2
96
97b5:                                               ; preds = %b4, %b0
98  ret void
99}
100
101; Function Attrs: nounwind readnone
102declare <16 x i32> @llvm.hexagon.V6.vd0() #1
103
104; Function Attrs: nounwind readnone
105declare <16 x i32> @llvm.hexagon.V6.lvsplatw(i32) #1
106
107; Function Attrs: nounwind readnone
108declare <16 x i32> @llvm.hexagon.V6.vpackeh(<16 x i32>, <16 x i32>) #1
109
110; Function Attrs: nounwind readnone
111declare <16 x i32> @llvm.hexagon.V6.vdelta(<16 x i32>, <16 x i32>) #1
112
113; Function Attrs: nounwind readnone
114declare <16 x i32> @llvm.hexagon.V6.vsubh(<16 x i32>, <16 x i32>) #1
115
116; Function Attrs: nounwind readnone
117declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat(<16 x i32>, <16 x i32>) #1
118
119; Function Attrs: nounwind readnone
120declare <16 x i32> @llvm.hexagon.V6.vdmpyhvsat.acc(<16 x i32>, <16 x i32>, <16 x i32>) #1
121
122; Function Attrs: nounwind readnone
123declare <16 x i32> @llvm.hexagon.V6.vasrw.acc(<16 x i32>, <16 x i32>, i32) #1
124
125attributes #0 = { nounwind "target-cpu"="hexagonv60" "target-features"="+hvxv60,+hvx-length64b" }
126attributes #1 = { nounwind readnone }
127
128!0 = !{!1, !1, i64 0}
129!1 = !{!"omnipotent char", !2, i64 0}
130!2 = !{!"Simple C/C++ TBAA"}
131!3 = !{!4, !4, i64 0}
132!4 = !{!"any pointer", !1, i64 0}
133