| /external/u-boot/arch/m68k/cpu/mcf5445x/ |
| D | speed.c | 74 int temp, vco = 0, bootmod_ccr, pdr; in setup_5441x_clocks() local
106 vco = ((in_be32(&pll->pcr) & PLL_CR_FBKDIV_BITS) + 1) * in setup_5441x_clocks()
108 gd->arch.vco_clk = vco; in setup_5441x_clocks()
114 gd->cpu_clk = vco / temp; /* cpu clock */ in setup_5441x_clocks()
115 gd->arch.flb_clk = vco / temp; /* FlexBus clock */ in setup_5441x_clocks()
121 gd->bus_clk = vco / temp; /* bus clock */ in setup_5441x_clocks()
133 int vco = 0, temp, fbtemp, pcrvalue; in setup_5445x_clocks() local
195 vco = pPllmult[ccm->rcon & fbpll_mask] * CONFIG_SYS_INPUT_CLKSRC; in setup_5445x_clocks()
197 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { in setup_5445x_clocks()
204 vco = i * CONFIG_SYS_INPUT_CLKSRC; in setup_5445x_clocks()
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| /external/u-boot/arch/arm/mach-socfpga/ |
| D | clock_manager_gen5.c | 106 &clock_manager_base->main_pll.vco); in cm_basic_init()
109 &clock_manager_base->per_pll.vco); in cm_basic_init()
112 &clock_manager_base->sdr_pll.vco); in cm_basic_init()
127 readl(&clock_manager_base->main_pll.vco); in cm_basic_init()
128 readl(&clock_manager_base->per_pll.vco); in cm_basic_init()
129 readl(&clock_manager_base->sdr_pll.vco); in cm_basic_init()
136 writel(cfg->main_vco_base, &clock_manager_base->main_pll.vco); in cm_basic_init()
137 writel(cfg->peri_vco_base, &clock_manager_base->per_pll.vco); in cm_basic_init()
138 writel(cfg->sdram_vco_base, &clock_manager_base->sdr_pll.vco); in cm_basic_init()
193 &clock_manager_base->main_pll.vco); in cm_basic_init()
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| D | clock_manager_s10.c | 175 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_main_vco_clk_hz() local
199 vco = fref / refdiv; in cm_get_main_vco_clk_hz()
200 vco = vco * (CLKMGR_MDIV_CONST + mdiv); in cm_get_main_vco_clk_hz()
201 return vco; in cm_get_main_vco_clk_hz()
206 unsigned long fref, refdiv, mdiv, reg, vco; in cm_get_per_vco_clk_hz() local
230 vco = fref / refdiv; in cm_get_per_vco_clk_hz()
231 vco = vco * (CLKMGR_MDIV_CONST + mdiv); in cm_get_per_vco_clk_hz()
232 return vco; in cm_get_per_vco_clk_hz()
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| D | clock_manager_arria10.c | 1016 u32 vco = 0; in cm_get_per_vco_clk_hz() local
1038 vco = readl(&clock_manager_base->per_pll.vco1); in cm_get_per_vco_clk_hz()
1040 numer = vco & CLKMGR_PERPLL_VCO1_NUMER_MSK; in cm_get_per_vco_clk_hz()
1042 denom = (vco >> CLKMGR_PERPLL_VCO1_DENOM_LSB) & in cm_get_per_vco_clk_hz()
1045 vco = src_hz; in cm_get_per_vco_clk_hz()
1046 vco /= 1 + denom; in cm_get_per_vco_clk_hz()
1047 vco *= 1 + numer; in cm_get_per_vco_clk_hz()
1049 return vco; in cm_get_per_vco_clk_hz()
1054 u32 src_hz, numer, denom, vco; in cm_get_main_vco_clk_hz() local
1072 vco = readl(&clock_manager_base->main_pll.vco1); in cm_get_main_vco_clk_hz()
[all …]
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| /external/u-boot/arch/m68k/cpu/mcf5227x/ |
| D | speed.c | 75 int vco, temp, pcrvalue, pfdr; in get_clocks() local
90 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
91 if ((vco < CLOCK_PLL_FVCO_MIN) || (vco > CLOCK_PLL_FVCO_MAX)) { in get_clocks()
96 vco = in get_clocks()
100 gd->arch.vco_clk = vco; /* Vco clock */ in get_clocks()
103 vco = ((in_be32(&pll->pcr) & 0xFF000000) >> 24) * CONFIG_SYS_INPUT_CLKSRC; in get_clocks()
104 gd->arch.vco_clk = vco; /* Vco clock */ in get_clocks()
113 gd->cpu_clk = vco / temp; /* cpu clock */ in get_clocks()
116 gd->arch.flb_clk = vco / temp; /* flexbus clock */ in get_clocks()
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| /external/u-boot/arch/arm/cpu/armv8/s32v234/ |
| D | generic.c | 30 u32 vco = 0, plldv_prediv = 0, plldv_mfd = 0, pllfd_mfn = 0; in get_pllfreq() local
47 vco = refclk_freq / plldv_prediv * (plldv_mfd + pllfd_mfn / 20481); in get_pllfreq()
64 fout = vco / (dfs_mfi + (dfs_mfn / 256)); in get_pllfreq()
66 fout = vco / plldv_rfdphi_div; in get_pllfreq()
74 fout = vco / plldv_rfdphi_div; in get_pllfreq()
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| /external/u-boot/arch/arm/mach-socfpga/include/mach/ |
| D | clock_manager_gen5.h | 49 u32 vco; member
67 u32 vco; member
84 u32 vco; member
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| /external/u-boot/drivers/clk/ |
| D | clk_stm32h7.c | 502 ulong vco, rate; in stm32_get_PLL1_rate() local
544 vco = (pllsrc / divm1) * divn1; in stm32_get_PLL1_rate()
550 __func__, fracn1, vco, rate); in stm32_get_PLL1_rate()
554 return (vco + rate) / divp1; in stm32_get_PLL1_rate()
557 return (vco + rate) / divq1; in stm32_get_PLL1_rate()
561 return (vco + rate) / divr1; in stm32_get_PLL1_rate()
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| D | clk_stm32f.c | 397 u32 vco; in stm32_clk_get_rate() local
412 vco = (priv->hse_rate / pllm) * plln; in stm32_clk_get_rate()
413 sysclk = vco / pllp; in stm32_clk_get_rate()
467 return (vco / pllq); in stm32_clk_get_rate()
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| /external/u-boot/arch/arm/mach-tegra/tegra124/ |
| D | clock.c | 1067 u32 cf, vco, rounded_rate = frequency; in clock_set_display_rate() local
1074 for (divp = 0, vco = frequency; vco < min_vco && divp < max_p; divp++) in clock_set_display_rate()
1075 vco <<= 1; in clock_set_display_rate()
1077 if (vco < min_vco || vco > max_vco) { in clock_set_display_rate()
1084 best_diff = vco; in clock_set_display_rate()
1093 divn = vco / cf; in clock_set_display_rate()
1097 diff = vco - divn * cf; in clock_set_display_rate()
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| /external/u-boot/doc/ |
| D | README.m54418twr | 87 CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
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| /external/u-boot/board/freescale/m54455evb/ |
| D | README | 134 CONFIG_EXTRA_CLOCK -- Enable extra clock such as vco, flexbus, pci, etc
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| /external/honggfuzz/examples/apache-httpd/corpus_http2/ |
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| /external/honggfuzz/examples/apache-httpd/corpus_http1/ |
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