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Searched refs:vform (Results 1 – 10 of 10) sorted by relevance

/external/vixl/src/aarch64/
Dlogic-aarch64.cc170 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1() argument
171 dst.ClearForWrite(vform); in ld1()
172 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld1()
173 dst.ReadUintFromMem(vform, i, addr); in ld1()
174 addr += LaneSizeInBytesFromFormat(vform); in ld1()
179 void Simulator::ld1(VectorFormat vform, in ld1() argument
183 dst.ReadUintFromMem(vform, index, addr); in ld1()
187 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1r() argument
188 dst.ClearForWrite(vform); in ld1r()
189 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld1r()
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Dinstructions-aarch64.cc399 VectorFormat VectorFormatHalfWidth(VectorFormat vform) { in VectorFormatHalfWidth() argument
400 VIXL_ASSERT(vform == kFormat8H || vform == kFormat4S || vform == kFormat2D || in VectorFormatHalfWidth()
401 vform == kFormatH || vform == kFormatS || vform == kFormatD); in VectorFormatHalfWidth()
402 switch (vform) { in VectorFormatHalfWidth()
422 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) { in VectorFormatDoubleWidth() argument
423 VIXL_ASSERT(vform == kFormat8B || vform == kFormat4H || vform == kFormat2S || in VectorFormatDoubleWidth()
424 vform == kFormatB || vform == kFormatH || vform == kFormatS); in VectorFormatDoubleWidth()
425 switch (vform) { in VectorFormatDoubleWidth()
445 VectorFormat VectorFormatFillQ(VectorFormat vform) { in VectorFormatFillQ() argument
446 switch (vform) { in VectorFormatFillQ()
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Dsimulator-aarch64.h207 int64_t Int(VectorFormat vform, int index) const { in Int() argument
209 switch (LaneSizeInBitsFromFormat(vform)) { in Int()
229 uint64_t Uint(VectorFormat vform, int index) const { in Uint() argument
231 switch (LaneSizeInBitsFromFormat(vform)) { in Uint()
251 uint64_t UintLeftJustified(VectorFormat vform, int index) const { in UintLeftJustified() argument
252 return Uint(vform, index) << (64 - LaneSizeInBitsFromFormat(vform)); in UintLeftJustified()
255 int64_t IntLeftJustified(VectorFormat vform, int index) const { in IntLeftJustified() argument
256 uint64_t value = UintLeftJustified(vform, index); in IntLeftJustified()
262 void SetInt(VectorFormat vform, int index, int64_t value) const { in SetInt() argument
263 switch (LaneSizeInBitsFromFormat(vform)) { in SetInt()
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Dinstructions-aarch64.h536 VectorFormat VectorFormatHalfWidth(VectorFormat vform);
537 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
538 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
539 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
541 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform);
542 VectorFormat VectorFormatFillQ(VectorFormat vform);
543 VectorFormat ScalarFormatFromFormat(VectorFormat vform);
544 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform);
545 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform);
547 unsigned LaneSizeInBitsFromFormat(VectorFormat vform);
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Dsimulator-aarch64.cc555 VectorFormat vform) { in GetPrintRegisterFormat() argument
556 switch (vform) { in GetPrintRegisterFormat()
590 VectorFormat vform) { in GetPrintRegisterFormatFP() argument
591 switch (vform) { in GetPrintRegisterFormatFP()
3297 VectorFormat vform; in VisitFPDataProcessing1Source() local
3302 vform = kFormatD; in VisitFPDataProcessing1Source()
3305 vform = kFormatS; in VisitFPDataProcessing1Source()
3308 vform = kFormatH; in VisitFPDataProcessing1Source()
3332 fabs_(vform, ReadVRegister(fd), ReadVRegister(fn)); in VisitFPDataProcessing1Source()
3334 LogVRegister(fd, GetPrintRegisterFormatFP(vform)); in VisitFPDataProcessing1Source()
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/external/v8/src/arm64/
Dsimulator-logic-arm64.cc347 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1() argument
348 dst.ClearForWrite(vform); in ld1()
349 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld1()
350 dst.ReadUintFromMem(vform, i, addr); in ld1()
351 addr += LaneSizeInBytesFromFormat(vform); in ld1()
355 void Simulator::ld1(VectorFormat vform, LogicVRegister dst, int index, in ld1() argument
357 dst.ReadUintFromMem(vform, index, addr); in ld1()
360 void Simulator::ld1r(VectorFormat vform, LogicVRegister dst, uint64_t addr) { in ld1r() argument
361 dst.ClearForWrite(vform); in ld1r()
362 for (int i = 0; i < LaneCountFromFormat(vform); i++) { in ld1r()
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Dsimulator-arm64.h390 int64_t Int(VectorFormat vform, int index) const { in Int() argument
392 switch (LaneSizeInBitsFromFormat(vform)) { in Int()
412 uint64_t Uint(VectorFormat vform, int index) const { in Uint() argument
414 switch (LaneSizeInBitsFromFormat(vform)) { in Uint()
434 uint64_t UintLeftJustified(VectorFormat vform, int index) const { in UintLeftJustified() argument
435 return Uint(vform, index) << (64 - LaneSizeInBitsFromFormat(vform)); in UintLeftJustified()
438 int64_t IntLeftJustified(VectorFormat vform, int index) const { in IntLeftJustified() argument
439 uint64_t value = UintLeftJustified(vform, index); in IntLeftJustified()
445 void SetInt(VectorFormat vform, int index, int64_t value) const { in SetInt() argument
446 switch (LaneSizeInBitsFromFormat(vform)) { in SetInt()
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Dinstructions-arm64.cc346 VectorFormat VectorFormatHalfWidth(VectorFormat vform) { in VectorFormatHalfWidth() argument
347 DCHECK(vform == kFormat8H || vform == kFormat4S || vform == kFormat2D || in VectorFormatHalfWidth()
348 vform == kFormatH || vform == kFormatS || vform == kFormatD); in VectorFormatHalfWidth()
349 switch (vform) { in VectorFormatHalfWidth()
367 VectorFormat VectorFormatDoubleWidth(VectorFormat vform) { in VectorFormatDoubleWidth() argument
368 DCHECK(vform == kFormat8B || vform == kFormat4H || vform == kFormat2S || in VectorFormatDoubleWidth()
369 vform == kFormatB || vform == kFormatH || vform == kFormatS); in VectorFormatDoubleWidth()
370 switch (vform) { in VectorFormatDoubleWidth()
388 VectorFormat VectorFormatFillQ(VectorFormat vform) { in VectorFormatFillQ() argument
389 switch (vform) { in VectorFormatFillQ()
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Dinstructions-arm64.h470 VectorFormat VectorFormatHalfWidth(VectorFormat vform);
471 VectorFormat VectorFormatDoubleWidth(VectorFormat vform);
472 VectorFormat VectorFormatDoubleLanes(VectorFormat vform);
473 VectorFormat VectorFormatHalfLanes(VectorFormat vform);
475 VectorFormat VectorFormatHalfWidthDoubleLanes(VectorFormat vform);
476 VectorFormat VectorFormatFillQ(VectorFormat vform);
477 VectorFormat ScalarFormatFromFormat(VectorFormat vform);
478 unsigned RegisterSizeInBitsFromFormat(VectorFormat vform);
479 unsigned RegisterSizeInBytesFromFormat(VectorFormat vform);
480 int LaneSizeInBytesFromFormat(VectorFormat vform);
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Dsimulator-arm64.cc711 void LogicVRegister::ReadUintFromMem(VectorFormat vform, int index, in ReadUintFromMem() argument
713 switch (LaneSizeInBitsFromFormat(vform)) { in ReadUintFromMem()
732 void LogicVRegister::WriteUintToMem(VectorFormat vform, int index, in WriteUintToMem() argument
734 switch (LaneSizeInBitsFromFormat(vform)) { in WriteUintToMem()
736 SimMemory::Write<uint8_t>(addr, static_cast<uint8_t>(Uint(vform, index))); in WriteUintToMem()
740 static_cast<uint16_t>(Uint(vform, index))); in WriteUintToMem()
744 static_cast<uint32_t>(Uint(vform, index))); in WriteUintToMem()
747 SimMemory::Write<uint64_t>(addr, Uint(vform, index)); in WriteUintToMem()
975 VectorFormat vform) { in GetPrintRegisterFormat() argument
976 switch (vform) { in GetPrintRegisterFormat()
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