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Searched refs:writew (Results 1 – 25 of 101) sorted by relevance

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/external/u-boot/board/renesas/sh7753evb/
Dsh7753evb.c28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio()
29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio()
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio()
31 writew(0x0000, &gpio->pdcr); /* SPI0 */ in init_gpio()
32 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio()
33 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio()
34 writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */ in init_gpio()
35 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio()
36 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio()
37 writew(0x0000, &gpio->pjcr); /* SCIF4 */ in init_gpio()
[all …]
/external/u-boot/board/renesas/sh7752evb/
Dsh7752evb.c28 writew(0x0000, &gpio->pacr); /* GETHER */ in init_gpio()
29 writew(0x0001, &gpio->pbcr); /* INTC */ in init_gpio()
30 writew(0x0000, &gpio->pccr); /* PWMU, INTC */ in init_gpio()
31 writew(0xeaff, &gpio->pecr); /* GPIO */ in init_gpio()
32 writew(0x0000, &gpio->pfcr); /* WDT */ in init_gpio()
33 writew(0x0000, &gpio->phcr); /* SPI1 */ in init_gpio()
34 writew(0x0000, &gpio->picr); /* SDHI */ in init_gpio()
35 writew(0x0003, &gpio->pkcr); /* SerMux */ in init_gpio()
36 writew(0x0000, &gpio->plcr); /* SerMux */ in init_gpio()
37 writew(0x0000, &gpio->pmcr); /* RIIC */ in init_gpio()
[all …]
/external/u-boot/drivers/i2c/
Domap24xx_i2c.c122 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/
130 writew(stat, &i2c_base->stat);
139 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/
173 writew(0xFFFF, &i2c_base->stat);
192 writew(I2C_STAT_RRDY, &i2c_base->stat);
252 writew(0, &i2c_base->con);
253 writew(psc, &i2c_base->psc);
254 writew(scll, &i2c_base->scll);
255 writew(sclh, &i2c_base->sclh);
256 writew(I2C_CON_EN, &i2c_base->con);
[all …]
/external/u-boot/arch/x86/cpu/queensbay/
Dtnc.c128 writew(PIRQE, &rcba->d02ir); in tnc_irq_init()
129 writew(PIRQF, &rcba->d03ir); in tnc_irq_init()
130 writew(PIRQG, &rcba->d27ir); in tnc_irq_init()
131 writew(PIRQH, &rcba->d31ir); in tnc_irq_init()
132 writew(PIRQA, &rcba->d23ir); in tnc_irq_init()
133 writew(PIRQB, &rcba->d24ir); in tnc_irq_init()
134 writew(PIRQC, &rcba->d25ir); in tnc_irq_init()
135 writew(PIRQD, &rcba->d26ir); in tnc_irq_init()
/external/u-boot/drivers/usb/musb/
Dmusb_hcd.c49 writew(csr, &musbr->txcsr); in write_toggle()
52 writew(csr, &musbr->txcsr); in write_toggle()
54 writew(csr, &musbr->txcsr); in write_toggle()
63 writew(csr, &musbr->rxcsr); in write_toggle()
67 writew(csr, &musbr->rxcsr); in write_toggle()
69 writew(csr, &musbr->rxcsr); in write_toggle()
88 writew(csr, &musbr->txcsr); in check_stall()
96 writew(csr, &musbr->txcsr); in check_stall()
103 writew(csr, &musbr->rxcsr); in check_stall()
125 writew(csr, &musbr->txcsr); in wait_until_ep0_ready()
[all …]
Dmusb_core.c27 writew(0, &musbr->intrtxe); in musb_start()
28 writew(0, &musbr->intrrxe); in musb_start()
52 writew(fifoaddr >> 3, &musbr->dir##fifoadd); \
85 writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); in musb_configure_ep()
89 writew(csr | MUSB_TXCSR_FLUSHFIFO, in musb_configure_ep()
98 writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); in musb_configure_ep()
102 writew(csr | MUSB_RXCSR_FLUSHFIFO, in musb_configure_ep()
Dmusb_udc.c213 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0_stall()
224 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0_ack_req()
233 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_ep0_tx_ready()
242 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_ep0_tx_ready_and_last()
251 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0_last()
282 writew(peri_rxcsr, &musbr->ep[ep].epN.rxcsr); in musb_peri_rx_ack()
291 writew(peri_txcsr, &musbr->ep[ep].epN.txcsr); in musb_peri_tx_ready()
605 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0()
610 writew(csr0, &musbr->ep[0].ep0.csr0); in musb_peri_ep0()
821 writew(peri_txcsr, &musbr->ep[ep].epN.txcsr); in udc_endpoint_write()
/external/u-boot/board/renesas/r7780mp/
Dr7780mp.c28 writew(0x0, PHCR); in board_init()
42 writew(0x432, FPGA_CFCTL); in ide_set_reset()
44 writew(inw(FPGA_CFPOW)|0x01, FPGA_CFPOW); in ide_set_reset()
46 writew(inw(FPGA_CFPOW)|0x02, FPGA_CFPOW); in ide_set_reset()
48 writew(0x01, FPGA_CFCDINTCLR); in ide_set_reset()
/external/u-boot/board/renesas/sh7763rdp/
Dsh7763rdp.c39 writew(inw(CPU_CMDREG)|0x0001, CPU_CMDREG); in board_init()
43 writew(((dat & ~0xff00) | 0x2400), PSEL1); in board_init()
44 writew(0, PFCR); in board_init()
45 writew(0, PGCR); in board_init()
46 writew(0, PHCR); in board_init()
/external/u-boot/board/ronetix/pm9263/
Dpm9263.c180 writew(1, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
181 writew(0x9d4f, PSRAM_CTRL_REG); /* write the BCR */ in pm9263_lcd_hw_psram_init()
186 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
188 writew(0x90, PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
195 writew(0x1234, PHYS_PSRAM); in pm9263_lcd_hw_psram_init()
196 writew(0x5678, PHYS_PSRAM + 2); in pm9263_lcd_hw_psram_init()
206 writew(0, PSRAM_CTRL_REG); /* 0 - RCR,1 - BCR */ in pm9263_lcd_hw_psram_init()
208 writew(0x90, PSRAM_CTRL_REG); in pm9263_lcd_hw_psram_init()
211 writew(0x1234, PHYS_PSRAM); in pm9263_lcd_hw_psram_init()
212 writew(0x5678, PHYS_PSRAM+2); in pm9263_lcd_hw_psram_init()
/external/u-boot/drivers/watchdog/
Dimx_watchdog.c18 writew(0x5555, &wdog->wsr); in hw_watchdog_reset()
19 writew(0xaaaa, &wdog->wsr); in hw_watchdog_reset()
36 writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | in hw_watchdog_init()
48 writew(0x5555, &wdog->wsr); in reset_cpu()
49 writew(0xaaaa, &wdog->wsr); /* load minimum 1/2 second timeout */ in reset_cpu()
/external/u-boot/arch/arm/cpu/arm926ejs/mx27/
Dreset.c29 writew(0x0000, &regs->wcr); in reset_cpu()
32 writew(0x5555, &regs->wsr); in reset_cpu()
33 writew(0xAAAA, &regs->wsr); in reset_cpu()
36 writew(WCR_WDE, &regs->wcr); in reset_cpu()
/external/u-boot/arch/arm/cpu/arm926ejs/mx25/
Dreset.c29 writew(0, &regs->wcr); in reset_cpu()
32 writew(WSR_UNLOCK1, &regs->wsr); in reset_cpu()
33 writew(WSR_UNLOCK2, &regs->wsr); in reset_cpu()
36 writew(WCR_WDE, &regs->wcr); in reset_cpu()
/external/u-boot/board/renesas/sh7757lcr/
Dsh7757lcr.c93 writew(0xa501, &pciebrg->ctrl_h8s); /* reset */ in init_pcie_bridge()
94 writew(0x0000, &pciebrg->cp_ctrl); in init_pcie_bridge()
95 writew(0x0000, &pciebrg->cp_addr); in init_pcie_bridge()
99 writew(tmp, &pciebrg->cp_data); in init_pcie_bridge()
102 writew(0xa500, &pciebrg->ctrl_h8s); /* start */ in init_pcie_bridge()
117 writew(0x0100, &phy->reset); /* set reset */ in init_usb_phy()
119 writew(0x0002, &phy->portsel); in init_usb_phy()
121 writew(0x0111, &phy->reset); /* clear reset */ in init_usb_phy()
123 writew(0x4000, &common0->suspmode); in init_usb_phy()
124 writew(0x4000, &common1->suspmode); in init_usb_phy()
/external/u-boot/board/ti/panda/
Dpanda.c81 writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0); in get_board_revision()
82 writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT); in get_board_revision()
93 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
95 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
97 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
111 writew((IEN | M3), (*ctrl)->control_padconf_core_base + in get_board_revision()
146 writew((IEN | M3), in is_panda_es_rev_b3()
/external/u-boot/arch/sh/lib/
Dtime_sh2.c23 writew(readw(CMSTR) | 0x01, CMSTR); in cmt_timer_start()
28 writew(readw(CMSTR) & ~0x01, CMSTR); in cmt_timer_stop()
36 writew(CMT_CMCSR_INIT, CMCSR_0); in timer_init()
40 writew(CMT_TIMER_RESET, CMCOR_0); in timer_init()
/external/u-boot/arch/arm/mach-imx/
Dinit.c77 writew(0, &wdog1->wmcr); in imx_wdog_disable_powerdown()
78 writew(0, &wdog2->wmcr); in imx_wdog_disable_powerdown()
81 writew(0, &wdog3->wmcr); in imx_wdog_disable_powerdown()
83 writew(0, &wdog4->wmcr); in imx_wdog_disable_powerdown()
/external/u-boot/arch/arm/mach-imx/mx8m/
Dsoc.c149 writew(enable, &wdog1->wmcr); in imx_set_wdog_powerdown()
150 writew(enable, &wdog2->wmcr); in imx_set_wdog_powerdown()
151 writew(enable, &wdog3->wmcr); in imx_set_wdog_powerdown()
219 writew((WCR_WDE | WCR_SRS), &wdog->wcr); in reset_cpu()
/external/u-boot/board/compulab/common/
Domap3_smc911x.c38 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in cl_omap3_smc911x_setup_net_chip_gmpc()
41 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in cl_omap3_smc911x_setup_net_chip_gmpc()
44 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in cl_omap3_smc911x_setup_net_chip_gmpc()
/external/u-boot/arch/arm/cpu/arm946es/
Dcpu.c59 writew(0x0, 0xfffece10); in reset_cpu()
60 writew(0x8, 0xfffece10); in reset_cpu()
/external/u-boot/drivers/net/
Dks8851_mll.c110 writew(offset | (BE0 << shift_bit), dev->iobase + 2); in ks_rdreg8()
117 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2); in ks_rdreg16()
127 writew(offset | (BE0 << shift_bit), dev->iobase + 2); in ks_wrreg8()
128 writew(value_write, dev->iobase); in ks_wrreg8()
133 writew(offset | ((BE1 | BE0) << (offset & 0x02)), dev->iobase + 2); in ks_wrreg16()
134 writew(val, dev->iobase); in ks_wrreg16()
163 writew(*wptr++, dev->iobase); in ks_outblk()
/external/u-boot/arch/x86/cpu/quark/
Dquark.c332 writew(PIRQC, &rcba->rmu_ir); in quark_irq_init()
333 writew(PIRQA | (PIRQB << 4) | (PIRQC << 8) | (PIRQD << 12), in quark_irq_init()
335 writew(PIRQD, &rcba->core_ir); in quark_irq_init()
336 writew(PIRQE | (PIRQF << 4) | (PIRQG << 8) | (PIRQH << 12), in quark_irq_init()
/external/u-boot/board/isee/igep00x0/
Digep00x0.c120 writew(readw(&ctrl_base->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe); in setup_net_chip()
122 writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe); in setup_net_chip()
124 writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00, in setup_net_chip()
/external/u-boot/drivers/mmc/
Dtegra_mmc.c92 writew((7 << 12) | (data->blocksize & 0xFFF), &priv->reg->blksize); in tegra_mmc_prepare_data()
93 writew(data->blocks, &priv->reg->blkcnt); in tegra_mmc_prepare_data()
120 writew(mode, &priv->reg->trnmod); in tegra_mmc_set_transfer_mode()
212 writew((cmd->cmdidx << 8) | flags, &priv->reg->cmdreg); in tegra_mmc_send_cmd_bounced()
376 writew(0, &priv->reg->clkcon); in tegra_mmc_change_clock()
388 writew(clk, &priv->reg->clkcon); in tegra_mmc_change_clock()
403 writew(clk, &priv->reg->clkcon); in tegra_mmc_change_clock()
/external/u-boot/arch/xtensa/include/asm/
Dio.h42 #define writew(b, addr) (void)((*(volatile unsigned short *)(addr)) = (b)) macro
49 #define __raw_writew writew
62 #define outw(val, port) writew((val), (u16 *)((unsigned long)(port)))

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