| /external/arm-optimized-routines/test/traces/ |
| D | sincosf.txt | 159 -0x1.d7dbf4p-10
160 0x1.d7dbf4p-10
161 -0x1.3e4a7p-14
163 -0x1.088c36p-9
164 0x1.fd3378p-10
165 -0x1.7f293cp-14
167 -0x1.0c0774p-9
168 0x1.000dfep-9
169 -0x1.88f704p-14
171 -0x1.0c7494p-9
[all …]
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| D | exp.txt | 1 0x1.0bc8e7ca4ae1bp+0
2 0x1.f9a012f44a109p-1
3 -0x1.87a0e64ca4704p-15
4 0x1.d2d48a18a7775p-1
5 0x1.bb1c1c3d91533p-1
6 -0x1.f99f18cd2896bp-16
7 0x1.58bb57317e405p-1
8 0x1.4a09091f7ebeep-1
9 -0x1.44718c44e91cfp-16
10 0x1.45fa2a0b71c2bp-1
[all …]
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| /external/libaom/libaom/av1/encoder/x86/ |
| D | av1_fwd_txfm2d_avx2.c | 48 __m256i x1[16]; in fdct16x16_new_avx2() local
49 btf_16_adds_subs_out_avx2(&x1[0], &x1[15], input[0], input[15]); in fdct16x16_new_avx2()
50 btf_16_adds_subs_out_avx2(&x1[1], &x1[14], input[1], input[14]); in fdct16x16_new_avx2()
51 btf_16_adds_subs_out_avx2(&x1[2], &x1[13], input[2], input[13]); in fdct16x16_new_avx2()
52 btf_16_adds_subs_out_avx2(&x1[3], &x1[12], input[3], input[12]); in fdct16x16_new_avx2()
53 btf_16_adds_subs_out_avx2(&x1[4], &x1[11], input[4], input[11]); in fdct16x16_new_avx2()
54 btf_16_adds_subs_out_avx2(&x1[5], &x1[10], input[5], input[10]); in fdct16x16_new_avx2()
55 btf_16_adds_subs_out_avx2(&x1[6], &x1[9], input[6], input[9]); in fdct16x16_new_avx2()
56 btf_16_adds_subs_out_avx2(&x1[7], &x1[8], input[7], input[8]); in fdct16x16_new_avx2()
59 btf_16_adds_subs_avx2(&x1[0], &x1[7]); in fdct16x16_new_avx2()
[all …]
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| /external/vixl/test/test-trace-reference/ |
| D | log-regs | 2 # x1: 0x~~~~~~~~~~~~~~~~
131 # x1: 0x~~~~~~~~~~~~~~~~
132 # x1: 0x~~~~~~~~~~~~~~~~
139 # x1: 0x~~~~~~~~~~~~~~~~
140 # x1: 0x~~~~~~~~~~~~~~~~
147 # x1: 0x~~~~~~~~~~~~~~~~
148 # x1: 0x~~~~~~~~~~~~~~~~
153 # x1: 0x~~~~~~~~~~~~~~~~
154 # x1: 0x~~~~~~~~~~~~~~~~
158 # x1: 0x~~~~~~~~~~~~~~~~
[all …]
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| /external/tcpdump/tests/ |
| D | telnet-iac-check-oobr.out | 2 …x1 0x1 0x8 0xa 0x7 0x1d 0xa8 0xd4 0x59 0x3c 0x88 0xa8 0xff 0xfe 0x24 0xff 0xfa 0x18 0x1 SE, SB 0x7…
|
| /external/llvm/test/Bitcode/ |
| D | bitwiseInstructions.3.2.ll | 8 define void @shl(i8 %x1){
10 ; CHECK: %res1 = shl i8 %x1, %x1
11 %res1 = shl i8 %x1, %x1
13 ; CHECK: %res2 = shl nuw i8 %x1, %x1
14 %res2 = shl nuw i8 %x1, %x1
16 ; CHECK: %res3 = shl nsw i8 %x1, %x1
17 %res3 = shl nsw i8 %x1, %x1
19 ; CHECK: %res4 = shl nuw nsw i8 %x1, %x1
20 %res4 = shl nuw nsw i8 %x1, %x1
25 define void @lshr(i8 %x1){
[all …]
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| D | binaryIntInstructions.3.2.ll | 8 define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){
10 ; CHECK: %res1 = add i1 %x1, %x1
11 %res1 = add i1 %x1, %x1
25 ; CHECK: %res6 = add nuw i1 %x1, %x1
26 %res6 = add nuw i1 %x1, %x1
28 ; CHECK: %res7 = add nsw i1 %x1, %x1
29 %res7 = add nsw i1 %x1, %x1
31 ; CHECK: %res8 = add nuw nsw i1 %x1, %x1
32 %res8 = add nuw nsw i1 %x1, %x1
37 define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){
[all …]
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| D | miscInstructions.3.2.ll | 18 define void @landingpadInstr1(i1 %cond1, <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2){
29 define void @landingpadInstr2(i1 %cond1, <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2){
40 define void @landingpadInstr3(i1 %cond1, <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2){
63 define void @selectInstr(i1 %cond1, <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2){
67 ; CHECK-NEXT: %res2 = select <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2
68 %res2 = select <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2
73 define void @icmp(i32 %x1, i32 %x2, i32* %ptr1, i32* %ptr2, <2 x i32> %vec1, <2 x i32> %vec2){
75 ; CHECK: %res1 = icmp eq i32 %x1, %x2
76 %res1 = icmp eq i32 %x1, %x2
78 ; CHECK-NEXT: %res2 = icmp ne i32 %x1, %x2
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/Bitcode/ |
| D | bitwiseInstructions.3.2.ll | 8 define void @shl(i8 %x1){
10 ; CHECK: %res1 = shl i8 %x1, %x1
11 %res1 = shl i8 %x1, %x1
13 ; CHECK: %res2 = shl nuw i8 %x1, %x1
14 %res2 = shl nuw i8 %x1, %x1
16 ; CHECK: %res3 = shl nsw i8 %x1, %x1
17 %res3 = shl nsw i8 %x1, %x1
19 ; CHECK: %res4 = shl nuw nsw i8 %x1, %x1
20 %res4 = shl nuw nsw i8 %x1, %x1
25 define void @lshr(i8 %x1){
[all …]
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| D | binaryIntInstructions.3.2.ll | 8 define void @add(i1 %x1, i8 %x2 ,i16 %x3, i32 %x4, i64 %x5){
10 ; CHECK: %res1 = add i1 %x1, %x1
11 %res1 = add i1 %x1, %x1
25 ; CHECK: %res6 = add nuw i1 %x1, %x1
26 %res6 = add nuw i1 %x1, %x1
28 ; CHECK: %res7 = add nsw i1 %x1, %x1
29 %res7 = add nsw i1 %x1, %x1
31 ; CHECK: %res8 = add nuw nsw i1 %x1, %x1
32 %res8 = add nuw nsw i1 %x1, %x1
37 define void @addvec8NuwNsw(<2 x i8> %x1, <3 x i8> %x2 ,<4 x i8> %x3, <8 x i8> %x4, <16 x i8> %x5){
[all …]
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| D | miscInstructions.3.2.ll | 18 define void @landingpadInstr1(i1 %cond1, <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2){
29 define void @landingpadInstr2(i1 %cond1, <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2){
40 define void @landingpadInstr3(i1 %cond1, <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2){
63 define void @selectInstr(i1 %cond1, <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2){
67 ; CHECK-NEXT: %res2 = select <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2
68 %res2 = select <2 x i1> %cond2, <2 x i8> %x1, <2 x i8> %x2
73 define void @icmp(i32 %x1, i32 %x2, i32* %ptr1, i32* %ptr2, <2 x i32> %vec1, <2 x i32> %vec2){
75 ; CHECK: %res1 = icmp eq i32 %x1, %x2
76 %res1 = icmp eq i32 %x1, %x2
78 ; CHECK-NEXT: %res2 = icmp ne i32 %x1, %x2
[all …]
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| /external/clang/test/SemaCXX/ |
| D | warn-bad-memaccess.cpp | 24 struct X1 { virtual void f(); } x1, x1arr[2]; variable
33 memset(&x1, 0, sizeof x1); // \ in test_warn()
44 memmove(&x1, 0, sizeof x1); // \ in test_warn()
47 memmove(0, &x1, sizeof x1); // \ in test_warn()
50 memcpy(&x1, 0, sizeof x1); // \ in test_warn()
53 memcpy(0, &x1, sizeof x1); // \ in test_warn()
56 memcmp(&x1, 0, sizeof x1); // \ in test_warn()
59 memcmp(0, &x1, sizeof x1); // \ in test_warn()
63 __builtin_memset(&x1, 0, sizeof x1); // \ in test_warn()
70 __builtin_memmove(&x1, 0, sizeof x1); // \ in test_warn()
[all …]
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| /external/llvm/test/MC/AArch64/ |
| D | arm64-simd-ldst.s | 4 ld1.8b {v0}, [x1]
5 ld1.8b {v0, v1}, [x1]
6 ld1.8b {v0, v1, v2}, [x1]
7 ld1.8b {v0, v1, v2, v3}, [x1]
9 ld1.8b {v3}, [x1]
14 ld1.16b {v0}, [x1]
15 ld1.16b {v0, v1}, [x1]
16 ld1.16b {v0, v1, v2}, [x1]
17 ld1.16b {v0, v1, v2, v3}, [x1]
19 ld1.4h {v0}, [x1]
[all …]
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| D | arm64-logical-encoding.s | 11 and x1, x2, #15
16 ands x1, x2, #15
21 ; CHECK: and x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0x92]
26 ; CHECK: ands x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0xf2]
29 eor x1, x2, #0x8000
32 ; CHECK: eor x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xd2]
35 orr x1, x2, #0x8000
38 ; CHECK: orr x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xb2]
51 and x1, x2, x3
53 and x1, x2, x3, lsl #2
[all …]
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| D | alias-addsubimm.s | 9 sub x1, x3, #2, lsl 12
10 add x1, x3, #-2, lsl 12
13 sub x1, x3, #4
14 add x1, x3, #-4
17 sub x1, x3, #4095, lsl 0
18 add x1, x3, #-4095, lsl 0
28 add x1, x3, #2, lsl 12
29 sub x1, x3, #-2, lsl 12
32 add x1, x3, #4
33 sub x1, x3, #-4
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AArch64/ |
| D | arm64-simd-ldst.s | 4 ld1.8b {v0}, [x1]
5 ld1.8b {v0, v1}, [x1]
6 ld1.8b {v0, v1, v2}, [x1]
7 ld1.8b {v0, v1, v2, v3}, [x1]
9 ld1.8b {v3}, [x1]
14 ld1.16b {v0}, [x1]
15 ld1.16b {v0, v1}, [x1]
16 ld1.16b {v0, v1, v2}, [x1]
17 ld1.16b {v0, v1, v2, v3}, [x1]
19 ld1.4h {v0}, [x1]
[all …]
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| D | arm64-logical-encoding.s | 11 and x1, x2, #15
16 ands x1, x2, #15
21 ; CHECK: and x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0x92]
26 ; CHECK: ands x1, x2, #0xf ; encoding: [0x41,0x0c,0x40,0xf2]
29 eor x1, x2, #0x8000
32 ; CHECK: eor x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xd2]
35 orr x1, x2, #0x8000
38 ; CHECK: orr x1, x2, #0x8000 ; encoding: [0x41,0x00,0x71,0xb2]
51 and x1, x2, x3
53 and x1, x2, x3, lsl #2
[all …]
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| D | alias-addsubimm.s | 22 sub x1, x3, #2, lsl 12
23 add x1, x3, #-2, lsl 12
27 sub x1, x3, #4
28 add x1, x3, #-4
32 sub x1, x3, #4095, lsl 0
33 add x1, x3, #-4095, lsl 0
45 add x1, x3, #2, lsl 12
46 sub x1, x3, #-2, lsl 12
50 add x1, x3, #4
51 sub x1, x3, #-4
[all …]
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AArch64/ |
| D | falkor-hwpf-fix.mir | 6 # CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
8 # CHECK: LDRWui $x1, 1
13 liveins: $w0, $x1
15 $w2 = LDRWui $x1, 0 :: ("aarch64-strided-access" load 4)
16 $w2 = LDRWui $x1, 1
27 # CHECK: $[[BASE:[a-z0-9]+]] = ORRXrs $xzr, $x1, 0
29 # CHECK: LDRWui $x1, 0
34 liveins: $w0, $x1, $q2
36 $q2 = LD1i64 $q2, 0, $x1 :: ("aarch64-strided-access" load 4)
37 $w2 = LDRWui $x1, 0
[all …]
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| D | machine-copy-remove.mir | 10 liveins: $x0, $x1
12 $x0 = COPY $x1
13 CBNZX $x1, %bb.2
20 liveins: $x1
22 $x0 = LDRXui $x1, 0
37 liveins: $x0, $x1
39 $x1 = COPY $x0
40 CBNZX $x1, %bb.2
47 liveins: $x1
49 $x0 = LDRXui $x1, 0
[all …]
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| /external/u-boot/arch/arm/cpu/armv8/fsl-layerscape/ |
| D | lowlevel.S | 33 ldr x1, =GICC_BASE
52 ldr x1, =GICC_BASE_64K
74 switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */
82 ldr x1, =0x00000010
98 ldr x1, =0x00000020
101 ldr x1, =0x00000020
108 ldr x1, =CCI_MN_RNF_NODEID_LIST
114 ldr x1, =0x00FF000C
117 ldr x1, =0x00FF000C
120 ldr x1, =0x00FF000C
[all …]
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| /external/libaom/libaom/av1/common/x86/ |
| D | av1_inv_txfm_avx2.c | 27 static INLINE void idct16_stage5_avx2(__m256i *x1, const int32_t *cospi, in idct16_stage5_avx2() argument
31 btf_16_adds_subs_avx2(&x1[0], &x1[3]); in idct16_stage5_avx2()
32 btf_16_adds_subs_avx2(&x1[1], &x1[2]); in idct16_stage5_avx2()
33 btf_16_w16_avx2(cospi_m32_p32, cospi_p32_p32, &x1[5], &x1[6], _r, cos_bit); in idct16_stage5_avx2()
35 btf_16_adds_subs_avx2(&x1[8], &x1[11]); in idct16_stage5_avx2()
36 btf_16_adds_subs_avx2(&x1[9], &x1[10]); in idct16_stage5_avx2()
37 btf_16_adds_subs_avx2(&x1[15], &x1[12]); in idct16_stage5_avx2()
38 btf_16_adds_subs_avx2(&x1[14], &x1[13]); in idct16_stage5_avx2()
53 static INLINE void idct16_stage7_avx2(__m256i *output, __m256i *x1) { in idct16_stage7_avx2() argument
54 btf_16_adds_subs_out_avx2(&output[0], &output[15], x1[0], x1[15]); in idct16_stage7_avx2()
[all …]
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| /external/libavc/common/armv8/ |
| D | ih264_intra_pred_luma_8x8_av8.s | 122 st1 {v0.8b}, [x1], x3
123 st1 {v0.8b}, [x1], x3
124 st1 {v0.8b}, [x1], x3
125 st1 {v0.8b}, [x1], x3
126 st1 {v0.8b}, [x1], x3
127 st1 {v0.8b}, [x1], x3
128 st1 {v0.8b}, [x1], x3
129 st1 {v0.8b}, [x1], x3
204 st1 {v0.8b}, [x1], x3
207 st1 {v1.8b}, [x1], x3
[all …]
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| D | ih264_padding_neon_av8.s | 89 sxtw x1, w1
92 sub x5, x0, x1
93 neg x6, x1
175 sxtw x1, w1
181 sub x6, x1, #16
186 add x0, x0, x1
188 add x0, x0, x1
191 add x0, x0, x1
192 st1 {v0.16b}, [x4], x1 // 16 bytes store
194 st1 {v2.16b}, [x4], x1 // 16 bytes store
[all …]
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| /external/epid-sdk/epid/member/tiny/math/src/ |
| D | fq2.c | 26 FqCp(&(result->x1), &(in->x1)); in Fq2Cp()
31 FqClear(&(result->x1)); in Fq2Set()
36 FqClear(&result->x1); in Fq2Clear()
41 FqAdd(&(result->x1), &(left->x1), &(right->x1)); in Fq2Add()
51 FqClear(&(temp->x1)); in Fq2Exp()
65 FqSub(&(result->x1), &(left->x1), &(right->x1)); in Fq2Sub()
74 FqAdd(a, &left->x0, &left->x1); in Fq2Mul()
75 FqAdd(b, &right->x0, &right->x1); in Fq2Mul()
79 FqMul(b, &left->x1, &right->x1); in Fq2Mul()
80 FqSub(&result->x1, a, b); in Fq2Mul()
[all …]
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