Home
last modified time | relevance | path

Searched full:xf (Results 1 – 25 of 2947) sorted by relevance

12345678910>>...118

/external/apache-commons-compress/src/test/java/org/apache/commons/compress/archivers/zip/
DX5455_ExtendedTimestampTest.java62 * The extended field (xf) we are testing.
64 private X5455_ExtendedTimestamp xf; field in X5455_ExtendedTimestampTest
70 xf = new X5455_ExtendedTimestamp(); in before()
142 … final X5455_ExtendedTimestamp xf = (X5455_ExtendedTimestamp) zae.getExtraField(X5455); in testSampleFile() local
144 final Date m = xf.getModifyJavaTime(); in testSampleFile()
160 final Date a = xf.getAccessJavaTime(); in testSampleFile()
201 assertFalse(xf.equals(new Object())); in testMisc()
202 assertTrue(xf.toString().startsWith("0x5455 Zip Extra Field")); in testMisc()
203 assertTrue(!xf.toString().contains(" Modify:")); in testMisc()
204 assertTrue(!xf.toString().contains(" Access:")); in testMisc()
[all …]
DX7875_NewUnixTest.java39 private X7875_NewUnix xf; field in X7875_NewUnixTest
43 xf = new X7875_NewUnix(); in before()
62 final X7875_NewUnix xf = (X7875_NewUnix) zae.getExtraField(X7875); in testSampleFile() local
81 assertEquals(expected, xf.getUID()); in testSampleFile()
82 assertEquals(expected, xf.getGID()); in testSampleFile()
93 assertEquals(X7875, xf.getHeaderId()); in testGetHeaderId()
98 assertFalse(xf.equals(new Object())); in testMisc()
99 assertTrue(xf.toString().startsWith("0x7875 Zip Extra Field")); in testMisc()
100 final Object o = xf.clone(); in testMisc()
101 assertEquals(o.hashCode(), xf.hashCode()); in testMisc()
[all …]
/external/u-boot/drivers/ddr/marvell/a38x/
Dddr3_training_ip_engine.c118 {0x1f, 0xf, 2, 0xf, 0x00680, 32}, /* PATTERN_STATIC_PBS */
119 {0x1f, 0xf, 2, 0xf, 0x00a80, 32}, /* PATTERN_KILLER_DQ0 */
120 {0x1f, 0xf, 2, 0xf, 0x01280, 32}, /* PATTERN_KILLER_DQ1 */
121 {0x1f, 0xf, 2, 0xf, 0x01a80, 32}, /* PATTERN_KILLER_DQ2 */
122 {0x1f, 0xf, 2, 0xf, 0x02280, 32}, /* PATTERN_KILLER_DQ3 */
123 {0x1f, 0xf, 2, 0xf, 0x02a80, 32}, /* PATTERN_KILLER_DQ4 */
124 {0x1f, 0xf, 2, 0xf, 0x03280, 32}, /* PATTERN_KILLER_DQ5 */
125 {0x1f, 0xf, 2, 0xf, 0x03a80, 32}, /* PATTERN_KILLER_DQ6 */
126 {0x1f, 0xf, 2, 0xf, 0x04280, 32}, /* PATTERN_KILLER_DQ7 */
127 {0x1f, 0xf, 2, 0xf, 0x00e80, 32}, /* PATTERN_KILLER_DQ0_64 */
[all …]
/external/libavc/common/
Dih264_common_tables.c443 { 0x0, 0x1, 0xc, 0x7, 0x1, 0x1, 0xf, 0x7, 0xc, 0xf, 0xc, 0x7, 0xf, 0x7, 0xf, 0x7 },
444 { 0x1, 0x1, 0xf, 0x7, 0x1, 0x1, 0xf, 0x7, 0xf, 0xf, 0xf, 0x7, 0xf, 0x7, 0xf, 0x7 },
445 { 0x2, 0x1, 0xc, 0x7, 0x1, 0x1, 0xf, 0x7, 0xc, 0xf, 0xc, 0x7, 0xf, 0x7, 0xf, 0x7 },
446 { 0x3, 0x1, 0xf, 0x7, 0x1, 0x1, 0xf, 0x7, 0xf, 0xf, 0xf, 0x7, 0xf, 0x7, 0xf, 0x7 },
448 { 0xc, 0xf, 0xc, 0x7, 0xf, 0x7, 0xf, 0x7, 0xc, 0xf, 0xc, 0x7, 0xf, 0x7, 0xf, 0x7 },
449 { 0xd, 0xf, 0xf, 0x7, 0xf, 0x7, 0xf, 0x7, 0xf, 0xf, 0xf, 0x7, 0xf, 0x7, 0xf, 0x7 },
450 { 0xe, 0xf, 0xc, 0x7, 0xf, 0x7, 0xf, 0x7, 0xc, 0xf, 0xc, 0x7, 0xf, 0x7, 0xf, 0x7 },
451 { 0xf, 0xf, 0xf, 0x7, 0xf, 0x7, 0xf, 0x7, 0xf, 0xf, 0xf, 0x7, 0xf, 0x7, 0xf, 0x7 },
453 { 0x0, 0x1, 0xc, 0x7, 0x1, 0x9, 0xf, 0x7, 0xc, 0xf, 0xc, 0x7, 0xf, 0x7, 0xf, 0x7 },
454 { 0x1, 0x1, 0xf, 0x7, 0x1, 0x9, 0xf, 0x7, 0xf, 0xf, 0xf, 0x7, 0xf, 0x7, 0xf, 0x7 },
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/Disassembler/AMDGPU/
Ddpp_vi.txt3 # VI: v_mov_b32_dpp v0, v0 quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x…
6 # VI: v_mov_b32_dpp v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x…
9 # VI: v_mov_b32_dpp v0, v0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
12 # VI: v_mov_b32_dpp v0, v0 row_ror:12 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
15 # VI: v_mov_b32_dpp v0, v0 wave_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
18 # VI: v_mov_b32_dpp v0, v0 wave_rol:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
21 # VI: v_mov_b32_dpp v0, v0 wave_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
24 # VI: v_mov_b32_dpp v0, v0 wave_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
27 # VI: v_mov_b32_dpp v0, v0 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
30 # VI: v_mov_b32_dpp v0, v0 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0…
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/MC/AMDGPU/
Dvop_dpp_expr.s9 // VI9: v_mov_b32_dpp v0, v0 quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,…
12 // VI9: v_mov_b32_dpp v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,…
15 // VI9: v_mov_b32_dpp v0, v0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e…
18 // VI9: v_mov_b32_dpp v0, v0 row_ror:12 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e…
21 // VI9: v_mov_b32_dpp v0, v0 wave_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e…
24 // VI9: v_mov_b32_dpp v0, v0 wave_rol:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e…
27 // VI9: v_mov_b32_dpp v0, v0 wave_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e…
30 // VI9: v_mov_b32_dpp v0, v0 wave_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e…
33 // VI9: v_mov_b32_dpp v0, v0 row_bcast:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x…
/external/llvm/test/MC/Disassembler/AMDGPU/
Ddpp_vi.txt3 # VI: v_mov_b32_dpp v0, v0 quad_perm:[0,2,1,1] row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x…
6 # VI: v_mov_b32_dpp v0, v0 row_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0x…
9 # VI: v_mov_b32_dpp v0, v0 row_shr:15 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
12 # VI: v_mov_b32_dpp v0, v0 row_ror:12 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
15 # VI: v_mov_b32_dpp v0, v0 wave_shl:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
18 # VI: v_mov_b32_dpp v0, v0 wave_rol:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
21 # VI: v_mov_b32_dpp v0, v0 wave_shr:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
24 # VI: v_mov_b32_dpp v0, v0 wave_ror:1 row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
27 # VI: v_mov_b32_dpp v0, v0 row_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0x7e,0…
30 # VI: v_mov_b32_dpp v0, v0 row_half_mirror row_mask:0xf bank_mask:0xf ; encoding: [0xfa,0x02,0x00,0…
[all …]
/external/u-boot/arch/arm/include/asm/arch-mx7/
Dmx7-ddr.h61 #define MSTR_DATA_ACTIVE_RANKS_MASK 0xf << 24
71 #define ADDRMAP2_COL_B2_MASK 0xF << 0
73 #define ADDRMAP2_COL_B3_MASK 0xF << 8
75 #define ADDRMAP2_COL_B4_MASK 0xF << 16
77 #define ADDRMAP2_COL_B5_MASK 0xF << 24
80 #define ADDRMAP3_COL_B6_MASK 0xF << 0
82 #define ADDRMAP3_COL_B7_MASK 0xF << 8
84 #define ADDRMAP3_COL_B8_MASK 0xF << 16
86 #define ADDRMAP3_COL_B9_MASK 0xF << 24
89 #define ADDRMAP4_COL_B10_MASK 0xF << 0
[all …]
/external/u-boot/arch/arm/mach-exynos/
Dclock.c32 {PERIPH_ID_UART0, 0xf, 0xf, -1, 0, 0, -1},
33 {PERIPH_ID_UART1, 0xf, 0xf, -1, 4, 4, -1},
34 {PERIPH_ID_UART2, 0xf, 0xf, -1, 8, 8, -1},
35 {PERIPH_ID_UART3, 0xf, 0xf, -1, 12, 12, -1},
44 {PERIPH_ID_SPI0, 0xf, 0xf, 0xff, 16, 0, 8},
45 {PERIPH_ID_SPI1, 0xf, 0xf, 0xff, 20, 16, 24},
46 {PERIPH_ID_SPI2, 0xf, 0xf, 0xff, 24, 0, 8},
47 {PERIPH_ID_SDMMC0, 0xf, 0xf, 0xff, 0, 0, 8},
48 {PERIPH_ID_SDMMC1, 0xf, 0xf, 0xff, 4, 16, 24},
49 {PERIPH_ID_SDMMC2, 0xf, 0xf, 0xff, 8, 0, 8},
[all …]
/external/vixl/src/aarch32/
Ddisasm-aarch32.cc95 if ((value & 0xf) == 0x1) { in Dt_L_imm6_1_Decode()
128 if ((value & 0xf) == 0x1) { in Dt_L_imm6_2_Decode()
141 if ((value & 0xf) == 0x1) { in Dt_L_imm6_3_Decode()
154 if ((value & 0xf) == 0x1) { in Dt_L_imm6_4_Decode()
7680 unsigned rm = (instr >> 19) & 0xf; in DecodeT32()
7693 unsigned rm = (instr >> 19) & 0xf; in DecodeT32()
7716 unsigned rm = (instr >> 19) & 0xf; in DecodeT32()
7724 unsigned rm = (instr >> 19) & 0xf; in DecodeT32()
7734 unsigned rm = (instr >> 19) & 0xf; in DecodeT32()
7744 unsigned rm = (instr >> 19) & 0xf; in DecodeT32()
[all …]
/external/u-boot/arch/arm/mach-at91/include/mach/
Datmel_mpddrc.h112 #define ATMEL_MPDDRC_TPR0_TRAS_MASK 0xf
114 #define ATMEL_MPDDRC_TPR0_TRCD_MASK 0xf
116 #define ATMEL_MPDDRC_TPR0_TWR_MASK 0xf
118 #define ATMEL_MPDDRC_TPR0_TRC_MASK 0xf
120 #define ATMEL_MPDDRC_TPR0_TRP_MASK 0xf
122 #define ATMEL_MPDDRC_TPR0_TRRD_MASK 0xf
128 #define ATMEL_MPDDRC_TPR0_TMRD_MASK 0xf
138 #define ATMEL_MPDDRC_TPR1_TXP_MASK 0xf
142 #define ATMEL_MPDDRC_TPR2_TXARD_MASK 0xf
144 #define ATMEL_MPDDRC_TPR2_TXARDS_MASK 0xf
[all …]
/external/mesa3d/src/mesa/main/
Dtexcompress_bptc.c294 0xf,0xf,0xf,0xf,0xf,0xf,0xf,0xf,0xf,0xf,0xf,0xf,0xf,0xf,0xf,0xf,
295 0xf,0x2,0x8,0x2,0x2,0x8,0x8,0xf,0x2,0x8,0x2,0x2,0x8,0x8,0x2,0x2,
296 0xf,0xf,0x6,0x8,0x2,0x8,0xf,0xf,0x2,0x8,0x2,0x2,0x2,0xf,0xf,0x6,
297 0x6,0x2,0x6,0x8,0xf,0xf,0x2,0x2,0xf,0xf,0xf,0xf,0xf,0x2,0x2,0xf
302 0x3,0x3,0xf,0xf,0x8,0x3,0xf,0xf,0x8,0x8,0x6,0x6,0x6,0x5,0x3,0x3,
303 0x3,0x3,0x8,0xf,0x3,0x3,0x6,0xa,0x5,0x8,0x8,0x6,0x8,0x5,0xf,0xf,
304 0x8,0xf,0x3,0x5,0x6,0xa,0x8,0xf,0xf,0x3,0xf,0x5,0xf,0xf,0xf,0xf,
305 0x3,0xf,0x5,0x5,0x5,0x8,0x5,0xa,0x5,0xa,0x8,0xd,0xf,0xc,0x3,0x3
312 0xf,0x8,0x8,0x3,0xf,0xf,0x3,0x8,0xf,0xf,0xf,0xf,0xf,0xf,0xf,0x8,
313 0xf,0x8,0xf,0x3,0xf,0x8,0xf,0x8,0x3,0xf,0x6,0xa,0xf,0xf,0xa,0x8,
[all …]
/external/u-boot/include/synopsys/
Ddwcddr21mctl.h74 #define DWCDDR21MCTL_DCR_CMD(x) (((x) & 0xf) << 27)
80 #define DWCDDR21MCTL_IOCR_RTT(x) (((x) & 0xf) << 0)
81 #define DWCDDR21MCTL_IOCR_DS(x) (((x) & 0xf) << 4)
103 #define DWCDDR21MCTL_DRR_RFBURST(x) (((x) & 0xf) << 24)
112 #define DWCDDR21MCTL_TPR0_TRP(x) (((x) & 0xf) << 8)
113 #define DWCDDR21MCTL_TPR0_TRCD(x) (((x) & 0xf) << 12)
115 #define DWCDDR21MCTL_TPR0_TRRD(x) (((x) & 0xf) << 21)
127 #define DWCDDR21MCTL_TPR1_XCL(x) (((x) & 0xf) << 23)
128 #define DWCDDR21MCTL_TPR1_XWR(x) (((x) & 0xf) << 27)
136 #define DWCDDR21MCTL_TPR2_TCKE(x) (((x) & 0xf) << 15)
[all …]
/external/mesa3d/src/gallium/drivers/nouveau/codegen/lib/
Dgm107.asm17 mov $r3 0x1 0xf
18 sched (st 0x1) (st 0xf wr 0x0) (st 0x6 wr 0x0 wt 0x1)
34 sched (st 0x6) (st 0x6 wr 0x0 rd 0x1 wt 0x1) (st 0xf wr 0x0 rd 0x1 wt 0x2)
35 mov $r3 $r0 0xf
46 sched (st 0x1) (st 0xf) (st 0xf)
62 sched (st 0xf wr 0x1) (st 0xd wr 0x1 wt 0x2) (st 0x1 wt 0x2)
66 sched (st 0x6) (st 0x1) (st 0xf wr 0x1)
67 mov $r3 0x1 0xf
84 mov $r3 $r0 0xf
86 sched (st 0xf wr 0x1 rd 0x2 wt 0x2) (st 0x6 wr 0x0 wt 0x5) (st 0xd wt 0x3)
[all …]
/external/u-boot/include/andestech/
Dandes_pcu.h86 #define ANDES_PCU_SPINFO_OFFSET(x) (((x) >> 8) & 0xf)
91 #define ANDES_PCU_SOC_ID_VER_MINOR(x) (((x) >> 0) & 0xf)
144 #define ANDES_PCU_DCSRCR0_LPC(x) (((x) & 0xf) << 8)
145 #define ANDES_PCU_DCSRCR0_ULPI(x) (((x) & 0xf) << 12)
146 #define ANDES_PCU_DCSRCR0_GMAC(x) (((x) & 0xf) << 16)
147 #define ANDES_PCU_DCSRCR0_GPU(x) (((x) & 0xf) << 20)
152 #define ANDES_PCU_DCSRCR1_I2C(x) (((x) & 0xf) << 0)
157 #define ANDES_PCU_DCSRCR2_UART1(x) (((x) & 0xf) << 0)
158 #define ANDES_PCU_DCSRCR2_UART2(x) (((x) & 0xf) << 4)
159 #define ANDES_PCU_DCSRCR2_AC97(x) (((x) & 0xf) << 8)
[all …]
/external/brotli/c/include/brotli/
Dport.h95 (((__SUNPRO_C >> 16) & 0xf) * 10) + ((__SUNPRO_C >> 12) & 0xf), \
96 (((__SUNPRO_C >> 8) & 0xf) * 10) + ((__SUNPRO_C >> 4) & 0xf), \
97 (__SUNPRO_C & 0xf) * 10)
100 BROTLI_MAKE_VERSION((__SUNPRO_C >> 8) & 0xf, \
101 (__SUNPRO_C >> 4) & 0xf, \
102 (__SUNPRO_C) & 0xf)
106 (((__SUNPRO_CC >> 16) & 0xf) * 10) + ((__SUNPRO_CC >> 12) & 0xf), \
107 (((__SUNPRO_CC >> 8) & 0xf) * 10) + ((__SUNPRO_CC >> 4) & 0xf), \
108 (__SUNPRO_CC & 0xf) * 10)
111 BROTLI_MAKE_VERSION((__SUNPRO_CC >> 8) & 0xf, \
[all …]
/external/mesa3d/src/gallium/drivers/swr/rasterizer/common/
Dsimdlib_128_avx512.inl50 #define SIMD_WRAPPER_1(op) SIMD_WRAPPER_1_(op, op, __mmask16(0xf))
58 #define SIMD_WRAPPER_1I(op) SIMD_WRAPPER_1I_(op, op, __mmask16(0xf))
65 #define SIMD_WRAPPER_2(op) SIMD_WRAPPER_2_(op, op, __mmask16(0xf))
71 return __conv(_mm512_maskz_##op(0xf, __conv(a), __conv(b), ImmT));\
79 #define SIMD_WRAPPER_3(op) SIMD_WRAPPER_3_(op, op, __mmask16(0xf))
93 #define SIMD_IWRAPPER_1_32(op) SIMD_IWRAPPER_1_(op, op, __mmask16(0xf))
101 #define SIMD_IWRAPPER_1I_32(op) SIMD_IWRAPPER_1I_(op, op, __mmask16(0xf))
108 #define SIMD_IWRAPPER_2_32(op) SIMD_IWRAPPER_2_(op, op, __mmask16(0xf))
114 return __conv(_mm512_maskz_##op(0xf, __conv(a), __conv(b), ImmT));\
127 SIMD_WRAPPER_1_(rcp_ps, rcp14_ps, __mmask16(0xf)); // return 1.0f / a
[all …]
/external/mesa3d/src/gallium/drivers/nouveau/nvc0/
Dnvc0_resource.h10 #define NVC0_TILE_SHIFT_X(m) ((((m) >> 0) & 0xf) + 6)
11 #define NVC0_TILE_SHIFT_Y(m) ((((m) >> 4) & 0xf) + 3)
12 #define NVC0_TILE_SHIFT_Z(m) ((((m) >> 8) & 0xf) + 0)
14 #define NVC0_TILE_SIZE_X(m) (64 << (((m) >> 0) & 0xf))
15 #define NVC0_TILE_SIZE_Y(m) ( 8 << (((m) >> 4) & 0xf))
16 #define NVC0_TILE_SIZE_Z(m) ( 1 << (((m) >> 8) & 0xf))
20 #define NVC0_TILE_SIZE_2D(m) ((64 * 8) << (((m) + ((m) >> 4)) & 0xf))
22 #define NVC0_TILE_SIZE(m) ((64 * 8) << (((m) + ((m) >> 4) + ((m) >> 8)) & 0xf))
/external/u-boot/arch/arm/include/asm/arch-mxs/
Dregs-lradc.h97 #define LRADC_CTRL2_TEMP_ISRC1_MASK (0xf << 4)
99 #define LRADC_CTRL2_TEMP_ISRC1_300 (0xf << 4)
115 #define LRADC_CTRL2_TEMP_ISRC0_MASK (0xf << 0)
117 #define LRADC_CTRL2_TEMP_ISRC0_300 (0xf << 0)
184 #define LRADC_DELAY_TRIGGER_DELAYS_MASK (0xf << 16)
214 #define LRADC_CTRL4_LRADC7SELECT_MASK (0xf << 28)
231 #define LRADC_CTRL4_LRADC7SELECT_CHANNEL15 (0xf << 28)
232 #define LRADC_CTRL4_LRADC6SELECT_MASK (0xf << 24)
249 #define LRADC_CTRL4_LRADC6SELECT_CHANNEL15 (0xf << 24)
250 #define LRADC_CTRL4_LRADC5SELECT_MASK (0xf << 20)
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/AMDGPU/
Dllvm.amdgcn.image.dim.ll6 ; GCN: image_load v[0:3], v0, s[0:7] dmask:0xf unorm{{$}}
14 ; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm{{$}}
22 ; GCN: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm{{$}}
30 ; GCN: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
38 ; GCN: image_load v[0:3], v[0:1], s[0:7] dmask:0xf unorm da{{$}}
46 ; GCN: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
54 ; GCN: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm{{$}}
62 ; GCN: image_load v[0:3], v[0:3], s[0:7] dmask:0xf unorm da{{$}}
70 ; GCN: image_load_mip v[0:3], v[0:1], s[0:7] dmask:0xf unorm{{$}}
78 ; GCN: image_load_mip v[0:3], v[0:3], s[0:7] dmask:0xf unorm{{$}}
[all …]
/external/u-boot/board/samsung/odroid/
Dsetup.h85 #define MUX_PWI_SEL(x) (((x) & 0xf) << 16)
95 /* #define PWI_SEL(x) (((x) & 0xf) << 16) - Reserved */
132 #define G2D_ACP_RATIO(x) ((x) & 0xf)
134 #define PWI_RATIO(x) (((x) & 0xf) << 8)
155 #define UART4_SEL(x) (((x) & 0xf) << 16)
156 #define UART3_SEL(x) (((x) & 0xf) << 12)
157 #define UART2_SEL(x) (((x) & 0xf) << 8)
158 #define UART1_SEL(x) (((x) & 0xf) << 4)
159 #define UART0_SEL(x) ((x) & 0xf)
162 #define UART4_RATIO(x) (((x) & 0xf) << 16)
[all …]
/external/mesa3d/src/gallium/drivers/radeonsi/
Dsi_state_msaa.c30 (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) | \
31 (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) | \
32 (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | \
33 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
98 val.idx = (sample_locs_2x[0] >> offset) & 0xf; in si_get_sample_position()
100 val.idx = (sample_locs_2x[0] >> (offset + 4)) & 0xf; in si_get_sample_position()
105 val.idx = (sample_locs_4x[0] >> offset) & 0xf; in si_get_sample_position()
107 val.idx = (sample_locs_4x[0] >> (offset + 4)) & 0xf; in si_get_sample_position()
113 val.idx = (sample_locs_8x[index] >> offset) & 0xf; in si_get_sample_position()
115 val.idx = (sample_locs_8x[index] >> (offset + 4)) & 0xf; in si_get_sample_position()
[all …]
/external/u-boot/arch/arm/include/asm/arch-omap3/
Domap3-regs.h43 #define CSONTIME(x) (((x) & 0xf) << 0)
49 #define ADVONTIME(x) (((x) & 0xf) << 0)
54 #define WEONTIME(x) (((x) & 0xf) << 16)
57 #define OEONTIME(x) (((x) & 0xf) << 0)
60 #define PAGEBURSTACCESSTIME(x) (((x) & 0xf) << 24)
67 #define WRDATAONADMUXBUS(x) (((x) & 0xf) << 16)
68 #define CYCLE2CYCLEDELAY(x) (((x) & 0xf) << 8)
71 #define BUSTURNAROUND(x) (((x) & 0xf) << 0)
74 #define MASKADDRESS(x) (((x) & 0xf) << 8)
/external/u-boot/arch/arm/include/asm/arch-vf610/
Dimx-regs.h142 #define DDRMC_CR14_TWTR(v) (((v) & 0xf) << 8)
145 #define DDRMC_CR16_TRTP(v) (((v) & 0xf) << 16)
167 #define DDRMC_CR34_CKSRX(v) (((v) & 0xf) << 16)
168 #define DDRMC_CR34_CKSRE(v) (((v) & 0xf) << 8)
179 #define DDRMC_CR69_ZQ_ON_SREF_EX(v) (((v) & 0xf) << 8)
182 #define DDRMC_CR73_APREBIT(v) (((v) & 0xf) << 24)
201 #define DDRMC_CR78_BUR_ON_FLY_BIT(v) ((v) & 0xf)
207 #define DDRMC_CR89_AODT_RWSMCS(v) ((v) & 0xf)
226 #define DDRMC_CR120_AXI0_PRI1_RPRI(v) (((v) & 0xf) << 24)
227 #define DDRMC_CR120_AXI0_PRI0_RPRI(v) (((v) & 0xf) << 16)
[all …]
/external/u-boot/arch/arm/include/asm/
Demif.h80 #define EMIF_REG_CL_MASK (0xf << 10)
118 #define EMIF_REG_T_RP_MASK (0xf << 25)
120 #define EMIF_REG_T_RCD_MASK (0xf << 21)
122 #define EMIF_REG_T_WR_MASK (0xf << 17)
134 #define EMIF_REG_T_RP_SHDW_MASK (0xf << 25)
136 #define EMIF_REG_T_RCD_SHDW_MASK (0xf << 21)
138 #define EMIF_REG_T_WR_SHDW_MASK (0xf << 17)
186 #define EMIF_REG_T_RAS_MAX_MASK (0xf << 0)
198 #define EMIF_REG_T_RAS_MAX_SHDW_MASK (0xf << 0)
206 #define EMIF_REG_NVM_T_RP_MASK (0xf << 20)
[all …]

12345678910>>...118