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Searched refs:reg (Results 1 – 25 of 144) sorted by relevance

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/art/compiler/utils/x86_64/
Dmanaged_register_x86_64_test.cc25 X86_64ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
26 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
27 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
31 X86_64ManagedRegister reg = X86_64ManagedRegister::FromCpuRegister(RAX); in TEST() local
32 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
33 EXPECT_TRUE(reg.IsCpuRegister()); in TEST()
34 EXPECT_TRUE(!reg.IsXmmRegister()); in TEST()
35 EXPECT_TRUE(!reg.IsX87Register()); in TEST()
36 EXPECT_TRUE(!reg.IsRegisterPair()); in TEST()
37 EXPECT_EQ(RAX, reg.AsCpuRegister()); in TEST()
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Dassembler_x86_64.h114 bool IsRegister(CpuRegister reg) const { in IsRegister() argument
116 && ((encoding_[0] & 0x07) == reg.LowBits()) // Register codes match. in IsRegister()
117 && (reg.NeedsRex() == ((rex_ & 1) != 0)); // REX.000B bits match. in IsRegister()
173 explicit Operand(CpuRegister reg) : rex_(0), length_(0), fixup_(nullptr) { SetModRM(3, reg); } in Operand() argument
363 void call(CpuRegister reg);
367 void pushq(CpuRegister reg);
371 void popq(CpuRegister reg);
611 void psllw(XmmRegister reg, const Immediate& shift_count);
612 void pslld(XmmRegister reg, const Immediate& shift_count);
613 void psllq(XmmRegister reg, const Immediate& shift_count);
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/art/compiler/utils/x86/
Dmanaged_register_x86_test.cc26 X86ManagedRegister reg = ManagedRegister::NoRegister().AsX86(); in TEST() local
27 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
28 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
32 X86ManagedRegister reg = X86ManagedRegister::FromCpuRegister(EAX); in TEST() local
33 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
34 EXPECT_TRUE(reg.IsCpuRegister()); in TEST()
35 EXPECT_TRUE(!reg.IsXmmRegister()); in TEST()
36 EXPECT_TRUE(!reg.IsX87Register()); in TEST()
37 EXPECT_TRUE(!reg.IsRegisterPair()); in TEST()
38 EXPECT_EQ(EAX, reg.AsCpuRegister()); in TEST()
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/art/compiler/utils/mips64/
Dmanaged_register_mips64_test.cc26 Mips64ManagedRegister reg = ManagedRegister::NoRegister().AsMips64(); in TEST() local
27 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
28 EXPECT_FALSE(reg.Overlaps(reg)); in TEST()
32 Mips64ManagedRegister reg = Mips64ManagedRegister::FromGpuRegister(ZERO); in TEST() local
33 EXPECT_FALSE(reg.IsNoRegister()); in TEST()
34 EXPECT_TRUE(reg.IsGpuRegister()); in TEST()
35 EXPECT_FALSE(reg.IsFpuRegister()); in TEST()
36 EXPECT_FALSE(reg.IsVectorRegister()); in TEST()
37 EXPECT_EQ(ZERO, reg.AsGpuRegister()); in TEST()
39 reg = Mips64ManagedRegister::FromGpuRegister(AT); in TEST()
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/art/compiler/utils/arm/
Dmanaged_register_arm_test.cc25 ArmManagedRegister reg = ManagedRegister::NoRegister().AsArm(); in TEST() local
26 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
27 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
31 ArmManagedRegister reg = ArmManagedRegister::FromCoreRegister(R0); in TEST() local
32 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
33 EXPECT_TRUE(reg.IsCoreRegister()); in TEST()
34 EXPECT_TRUE(!reg.IsSRegister()); in TEST()
35 EXPECT_TRUE(!reg.IsDRegister()); in TEST()
36 EXPECT_TRUE(!reg.IsRegisterPair()); in TEST()
37 EXPECT_EQ(R0, reg.AsCoreRegister()); in TEST()
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/art/compiler/debug/
Delf_debug_frame_writer.h45 for (int reg = 0; reg < 13; reg++) { in WriteCIE() local
46 if (reg < 4 || reg == 12) { in WriteCIE()
47 opcodes.Undefined(Reg::ArmCore(reg)); in WriteCIE()
49 opcodes.SameValue(Reg::ArmCore(reg)); in WriteCIE()
53 for (int reg = 0; reg < 32; reg++) { in WriteCIE() local
54 if (reg < 16) { in WriteCIE()
55 opcodes.Undefined(Reg::ArmFp(reg)); in WriteCIE()
57 opcodes.SameValue(Reg::ArmFp(reg)); in WriteCIE()
68 for (int reg = 0; reg < 30; reg++) { in WriteCIE() local
69 if (reg < 8 || reg == 16 || reg == 17) { in WriteCIE()
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/art/compiler/utils/arm64/
Dmanaged_register_arm64_test.cc27 Arm64ManagedRegister reg = ManagedRegister::NoRegister().AsArm64(); in TEST() local
28 EXPECT_TRUE(reg.IsNoRegister()); in TEST()
29 EXPECT_TRUE(!reg.Overlaps(reg)); in TEST()
34 Arm64ManagedRegister reg = Arm64ManagedRegister::FromXRegister(X0); in TEST() local
36 EXPECT_TRUE(!reg.IsNoRegister()); in TEST()
37 EXPECT_TRUE(reg.IsXRegister()); in TEST()
38 EXPECT_TRUE(!reg.IsWRegister()); in TEST()
39 EXPECT_TRUE(!reg.IsDRegister()); in TEST()
40 EXPECT_TRUE(!reg.IsSRegister()); in TEST()
41 EXPECT_TRUE(reg.Overlaps(wreg)); in TEST()
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Dassembler_arm64.cc106 static inline dwarf::Reg DWARFReg(CPURegister reg) { in DWARFReg() argument
107 if (reg.IsFPRegister()) { in DWARFReg()
108 return dwarf::Reg::Arm64Fp(reg.GetCode()); in DWARFReg()
110 DCHECK_LT(reg.GetCode(), 31u); // X0 - X30. in DWARFReg()
111 return dwarf::Reg::Arm64Core(reg.GetCode()); in DWARFReg()
169 void Arm64Assembler::PoisonHeapReference(Register reg) { in PoisonHeapReference() argument
170 DCHECK(reg.IsW()); in PoisonHeapReference()
172 ___ Neg(reg, Operand(reg)); in PoisonHeapReference()
175 void Arm64Assembler::UnpoisonHeapReference(Register reg) { in UnpoisonHeapReference() argument
176 DCHECK(reg.IsW()); in UnpoisonHeapReference()
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/art/runtime/arch/x86_64/
Dcontext_x86_64.h52 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in IsAccessibleGPR()
54 return gprs_[reg] != nullptr; in IsAccessibleGPR()
57 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
58 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPRAddress()
59 return gprs_[reg]; in GetGPRAddress()
62 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
63 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPR()
64 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
65 return *gprs_[reg]; in GetGPR()
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Dasm_support_x86_64.S75 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
76 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
77 #define CFI_RESTORE(reg) .cfi_restore reg argument
78 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
86 #define CFI_DEF_CFA(reg,size) argument
87 #define CFI_DEF_CFA_REGISTER(reg) argument
88 #define CFI_RESTORE(reg) argument
89 #define CFI_REL_OFFSET(reg,size) argument
137 MACRO1(PUSH, reg)
138 pushq REG_VAR(reg)
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/art/runtime/arch/arm/
Dcontext_arm.h53 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
54 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in IsAccessibleGPR()
55 return gprs_[reg] != nullptr; in IsAccessibleGPR()
58 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
59 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPRAddress()
60 return gprs_[reg]; in GetGPRAddress()
63 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
64 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPR()
65 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
66 return *gprs_[reg]; in GetGPR()
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/art/runtime/arch/arm64/
Dcontext_arm64.h53 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
54 DCHECK_LT(reg, arraysize(gprs_)); in IsAccessibleGPR()
55 return gprs_[reg] != nullptr; in IsAccessibleGPR()
58 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
59 DCHECK_LT(reg, arraysize(gprs_)); in GetGPRAddress()
60 return gprs_[reg]; in GetGPRAddress()
63 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
65 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfXRegisters)); in GetGPR()
66 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
67 return *gprs_[reg]; in GetGPR()
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/art/runtime/arch/mips64/
Dcontext_mips64.h48 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
49 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters)); in IsAccessibleGPR()
50 return gprs_[reg] != nullptr; in IsAccessibleGPR()
53 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
54 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters)); in GetGPRAddress()
55 return gprs_[reg]; in GetGPRAddress()
58 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
59 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfGpuRegisters)); in GetGPR()
60 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
61 return *gprs_[reg]; in GetGPR()
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/art/runtime/arch/mips/
Dcontext_mips.h48 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
49 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in IsAccessibleGPR()
50 return gprs_[reg] != nullptr; in IsAccessibleGPR()
53 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
54 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPRAddress()
55 return gprs_[reg]; in GetGPRAddress()
58 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
59 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCoreRegisters)); in GetGPR()
60 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
61 return *gprs_[reg]; in GetGPR()
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/art/runtime/arch/x86/
Dcontext_x86.h52 bool IsAccessibleGPR(uint32_t reg) override { in IsAccessibleGPR() argument
53 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in IsAccessibleGPR()
54 return gprs_[reg] != nullptr; in IsAccessibleGPR()
57 uintptr_t* GetGPRAddress(uint32_t reg) override { in GetGPRAddress() argument
58 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPRAddress()
59 return gprs_[reg]; in GetGPRAddress()
62 uintptr_t GetGPR(uint32_t reg) override { in GetGPR() argument
63 DCHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in GetGPR()
64 DCHECK(IsAccessibleGPR(reg)); in GetGPR()
65 return *gprs_[reg]; in GetGPR()
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Dasm_support_x86.S76 #define CFI_DEF_CFA(reg,size) .cfi_def_cfa reg,size argument
77 #define CFI_DEF_CFA_REGISTER(reg) .cfi_def_cfa_register reg argument
78 #define CFI_RESTORE(reg) .cfi_restore reg argument
79 #define CFI_REL_OFFSET(reg,size) .cfi_rel_offset reg,size argument
88 #define CFI_DEF_CFA(reg,size) argument
89 #define CFI_DEF_CFA_REGISTER(reg) argument
90 #define CFI_RESTORE(reg) argument
91 #define CFI_REL_OFFSET(reg,size) argument
139 MACRO1(PUSH, reg)
140 pushl REG_VAR(reg)
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Dcontext_x86.cc77 void X86Context::SetGPR(uint32_t reg, uintptr_t value) { in SetGPR() argument
78 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfCpuRegisters)); in SetGPR()
79 DCHECK(IsAccessibleGPR(reg)); in SetGPR()
80 CHECK_NE(gprs_[reg], &gZero); in SetGPR()
81 *gprs_[reg] = value; in SetGPR()
84 void X86Context::SetFPR(uint32_t reg, uintptr_t value) { in SetFPR() argument
85 CHECK_LT(reg, static_cast<uint32_t>(kNumberOfFloatRegisters)); in SetFPR()
86 DCHECK(IsAccessibleFPR(reg)); in SetFPR()
87 CHECK_NE(fprs_[reg], reinterpret_cast<const uint32_t*>(&gZero)); in SetFPR()
88 *fprs_[reg] = value; in SetFPR()
/art/runtime/
Ddex_register_location.cc25 std::ostream& operator<<(std::ostream& stream, const DexRegisterLocation& reg) { in operator <<() argument
27 switch (reg.GetKind()) { in operator <<()
33 return stream << "sp+" << reg.GetValue(); in operator <<()
35 return stream << "r" << reg.GetValue(); in operator <<()
37 return stream << "r" << reg.GetValue() << "/hi"; in operator <<()
39 return stream << "f" << reg.GetValue(); in operator <<()
41 return stream << "f" << reg.GetValue() << "/hi"; in operator <<()
43 return stream << "#" << reg.GetValue(); in operator <<()
45 return stream << "DexRegisterLocation(" << static_cast<uint32_t>(reg.GetKind()) in operator <<()
46 << "," << reg.GetValue() << ")"; in operator <<()
/art/test/404-optimizing-allocator/src/
DMain.java23 expectEquals(4, $opt$reg$TestLostCopy()); in main()
24 expectEquals(-10, $opt$reg$TestTwoLive()); in main()
25 expectEquals(-20, $opt$reg$TestThreeLive()); in main()
26 expectEquals(5, $opt$reg$TestFourLive()); in main()
27 expectEquals(10, $opt$reg$TestMultipleLive()); in main()
28 expectEquals(1, $opt$reg$TestWithBreakAndContinue()); in main()
29 expectEquals(-15, $opt$reg$testSpillInIf(5, 6, 7)); in main()
30 expectEquals(-567, $opt$reg$TestAgressiveLive1(1, 2, 3, 4, 5, 6, 7)); in main()
31 expectEquals(-77, $opt$reg$TestAgressiveLive2(1, 2, 3, 4, 5, 6, 7)); in main()
34 public static int $opt$reg$TestLostCopy() { in $opt$reg$TestLostCopy()
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/art/libelffile/dwarf/
Ddebug_frame_opcode_writer.h73 void ALWAYS_INLINE RelOffset(Reg reg, int offset) { in RelOffset() argument
74 Offset(reg, offset - current_cfa_offset_); in RelOffset()
117 void ALWAYS_INLINE Offset(Reg reg, int offset) { in Offset() argument
122 if (0 <= reg.num() && reg.num() <= 0x3F) { in Offset()
123 this->PushUint8(DW_CFA_offset | reg.num()); in Offset()
127 this->PushUleb128(reg.num()); in Offset()
133 this->PushUleb128(reg.num()); in Offset()
139 void ALWAYS_INLINE Restore(Reg reg) { in Restore() argument
142 if (0 <= reg.num() && reg.num() <= 0x3F) { in Restore()
143 this->PushUint8(DW_CFA_restore | reg.num()); in Restore()
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/art/runtime/arch/
Dcontext.h64 virtual bool IsAccessibleGPR(uint32_t reg) = 0;
67 virtual uintptr_t* GetGPRAddress(uint32_t reg) = 0;
71 virtual uintptr_t GetGPR(uint32_t reg) = 0;
75 virtual void SetGPR(uint32_t reg, uintptr_t value) = 0;
78 virtual bool IsAccessibleFPR(uint32_t reg) = 0;
82 virtual uintptr_t GetFPR(uint32_t reg) = 0;
86 virtual void SetFPR(uint32_t reg, uintptr_t value) = 0;
/art/runtime/interpreter/mterp/arm/
Dmain.S199 .macro FETCH_ADVANCE_INST_RB reg argument
200 ldrh rINST, [rPC, \reg]!
209 .macro FETCH reg, count
210 ldrh \reg, [rPC, #((\count)*2)]
213 .macro FETCH_S reg, count
214 ldrsh \reg, [rPC, #((\count)*2)]
222 .macro FETCH_B reg, count, byte
223 ldrb \reg, [rPC, #((\count)*2+(\byte))]
229 .macro GET_INST_OPCODE reg argument
230 and \reg, rINST, #255
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/art/runtime/interpreter/mterp/arm64/
Dmain.S193 .macro FETCH_ADVANCE_INST_RB reg argument
194 add xPC, xPC, \reg, sxtw
204 .macro FETCH reg, count
205 ldrh \reg, [xPC, #((\count)*2)]
208 .macro FETCH_S reg, count
209 ldrsh \reg, [xPC, #((\count)*2)]
217 .macro FETCH_B reg, count, byte
218 ldrb \reg, [xPC, #((\count)*2+(\byte))]
224 .macro GET_INST_OPCODE reg argument
225 and \reg, xINST, #255
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/art/libdexfile/dex/
Ddex_file-inl.h248 for (uint16_t reg = 0; reg < registers_size; reg++) { in DecodeDebugLocalInfo() local
249 if (local_in_reg[reg].is_live_) { in DecodeDebugLocalInfo()
250 local_in_reg[reg].end_address_ = insns_size_in_code_units; in DecodeDebugLocalInfo()
251 new_local_callback(local_in_reg[reg]); in DecodeDebugLocalInfo()
263 uint16_t reg = DecodeUnsignedLeb128(&stream); in DecodeDebugLocalInfo() local
264 if (reg >= registers_size) { in DecodeDebugLocalInfo()
265 LOG(ERROR) << "invalid stream - reg >= reg size (" << reg << " >= " in DecodeDebugLocalInfo()
278 if (local_in_reg[reg].is_live_) { in DecodeDebugLocalInfo()
279 local_in_reg[reg].end_address_ = address; in DecodeDebugLocalInfo()
280 new_local_callback(local_in_reg[reg]); in DecodeDebugLocalInfo()
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/art/runtime/interpreter/mterp/mips64/
Dmain.S168 .macro FETCH_ADVANCE_INST_RB reg argument
169 daddu rPC, rPC, \reg
198 .macro GET_INST_OPCODE reg argument
199 and \reg, rINST, 255
205 .macro GOTO_OPCODE reg argument
207 sll AT, \reg, 7
220 .macro GET_VREG reg, vreg
223 lw \reg, 0(AT)
226 .macro GET_VREG_U reg, vreg
229 lwu \reg, 0(AT)
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