Searched refs:Ld0 (Results 1 – 3 of 3) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/ARM/ |
| D | ARMParallelDSP.cpp | 121 bool AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, MemInstList &VecMem);
306 bool ARMParallelDSP::AreSequentialLoads(LoadInst *Ld0, LoadInst *Ld1, in AreSequentialLoads() argument
308 if (!Ld0 || !Ld1) in AreSequentialLoads()
312 dbgs() << "Ld0:"; Ld0->dump(); in AreSequentialLoads()
316 if (!Ld0->hasOneUse() || !Ld1->hasOneUse()) { in AreSequentialLoads()
321 return AreSequentialAccesses<LoadInst>(Ld0, Ld1, VecMem, *DL, *SE); in AreSequentialLoads()
363 auto *Ld0 = dyn_cast<LoadInst>(Mul0_LHS[x]); in CreateParallelMACPairs() local
375 if (AreSequentialLoads(Ld0, Ld1, PMul0->VecLd) && in CreateParallelMACPairs()
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| /external/swiftshader/third_party/llvm-7.0/llvm/test/CodeGen/Hexagon/autohvx/ |
| D | shuff-combos-64b.ll | 186 ; CHECK: v[[Hd0:[0-9]+]]:[[Ld0:[0-9]+]] = vshuff(v1,v0,[[Rd0]])
187 ; CHECK: v[[Hd1:[0-9]+]]:[[Ld1:[0-9]+]] = vdeal(v[[Hd0]],v[[Ld0]],[[Rd1]])
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| D | shuff-combos-128b.ll | 200 ; CHECK: v[[Hd0:[0-9]+]]:[[Ld0:[0-9]+]] = vshuff(v1,v0,[[Rd0]])
201 ; CHECK: v[[Hd1:[0-9]+]]:[[Ld1:[0-9]+]] = vshuff(v[[Hd0]],v[[Ld0]],[[Rd1]])
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