| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/ |
| D | X86ShuffleDecodeConstantPool.cpp | 79 APInt MaskBits(CstSizeInBits, 0); in extractConstantMask() local
92 MaskBits.insertBits(cast<ConstantInt>(COp)->getValue(), BitOffset); in extractConstantMask()
108 APInt EltBits = MaskBits.extractBits(MaskEltSizeInBits, BitOffset); in extractConstantMask()
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| D | X86ISelLowering.cpp | 5541 APInt MaskBits(SizeInBits, 0); in getTargetConstantBitsFromNode() local
5547 MaskBits.insertBits(SrcEltBits[i], BitOffset); in getTargetConstantBitsFromNode()
5571 APInt Bits = MaskBits.extractBits(EltSizeInBits, BitOffset); in getTargetConstantBitsFromNode()
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| /external/mesa3d/src/intel/vulkan/ |
| D | genX_state.c | 105 ps.MaskBits = 3; in genX()
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| D | genX_cmd_buffer.c | 2851 ps.MaskBits = 3; in genX()
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| /external/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 2683 unsigned MaskBits; in isAArch64FrameOffsetLegal() local
2686 MaskBits = 7; in isAArch64FrameOffsetLegal()
2689 MaskBits = 9; in isAArch64FrameOffsetLegal()
2693 MaskBits = 12; in isAArch64FrameOffsetLegal()
2699 int MaxOff = (1 << (MaskBits - IsSigned)) - 1; in isAArch64FrameOffsetLegal()
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| D | AArch64ISelLowering.cpp | 5162 unsigned MaskBits = APInt(32, NumElts * 2).logBase2(); in isEXTMask() local
5163 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1); in isEXTMask()
9530 unsigned MaskBits = 0; in performCONDCombine() local
9538 MaskBits = 8; in performCONDCombine()
9540 MaskBits = 16; in performCONDCombine()
9543 if (!MaskBits) in performCONDCombine()
9566 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) || in performCONDCombine()
9567 !checkValueWidth(AddInputValue2, MaskBits, ExtType) || in performCONDCombine()
9568 !checkValueWidth(AddInputValue1, MaskBits, ExtType) ) in performCONDCombine()
9571 if(!isEquivalentMaskless(CC, MaskBits, ExtType, in performCONDCombine()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AArch64/ |
| D | AArch64InstrInfo.cpp | 3393 unsigned MaskBits; in isAArch64FrameOffsetLegal() local
3396 MaskBits = 7; in isAArch64FrameOffsetLegal()
3399 MaskBits = 9; in isAArch64FrameOffsetLegal()
3403 MaskBits = 12; in isAArch64FrameOffsetLegal()
3409 int MaxOff = (1 << (MaskBits - IsSigned)) - 1; in isAArch64FrameOffsetLegal()
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| D | AArch64ISelLowering.cpp | 5946 unsigned MaskBits = APInt(32, NumElts * 2).logBase2(); in isEXTMask() local
5947 APInt ExpectedElt = APInt(MaskBits, *FirstRealElt + 1); in isEXTMask()
10549 unsigned MaskBits = 0; in performCONDCombine() local
10557 MaskBits = 8; in performCONDCombine()
10559 MaskBits = 16; in performCONDCombine()
10562 if (!MaskBits) in performCONDCombine()
10585 if (!checkValueWidth(SubsInputValue, MaskBits, ExtType) || in performCONDCombine()
10586 !checkValueWidth(AddInputValue2, MaskBits, ExtType) || in performCONDCombine()
10587 !checkValueWidth(AddInputValue1, MaskBits, ExtType) ) in performCONDCombine()
10590 if(!isEquivalentMaskless(CC, MaskBits, ExtType, in performCONDCombine()
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| /external/clang/lib/CodeGen/ |
| D | CGExprScalar.cpp | 1000 Value *MaskBits = in VisitShuffleVectorExpr() local
1002 Mask = Builder.CreateAnd(Mask, MaskBits, "mask"); in VisitShuffleVectorExpr()
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| /external/clang/include/clang/AST/ |
| D | Expr.h | 1786 enum { MaskBits = 2, Mask = 0x03 }; enumerator
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 2970 unsigned MaskBits = AndMask.countTrailingOnes(); in visitANDLike() local
2976 (ShiftBits + MaskBits <= Size / 2) && in visitANDLike()
2988 assert(ShiftBits != 0 && MaskBits <= Size); in visitANDLike()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/SelectionDAG/ |
| D | DAGCombiner.cpp | 4001 unsigned MaskBits = AndMask.countTrailingOnes(); in visitANDLike() local
4007 (ShiftBits + MaskBits <= Size / 2) && in visitANDLike()
4019 assert(MaskBits <= Size); in visitANDLike()
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