Searched refs:MemAccessSize (Results 1 – 14 of 14) sorted by relevance
| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrFormats.td | 23 class MemAccessSize<bits<4> value> {
27 // These numbers must match the MemAccessSize enumeration values in
29 def NoMemAccess : MemAccessSize<0>;
30 def ByteAccess : MemAccessSize<1>;
31 def HalfWordAccess : MemAccessSize<2>;
32 def WordAccess : MemAccessSize<3>;
33 def DoubleWordAccess : MemAccessSize<4>;
34 def HVXVectorAccess : MemAccessSize<5>;
139 MemAccessSize accessSize = NoMemAccess;
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| D | HexagonOptAddrMode.cpp | 327 case HexagonII::MemAccessSize::DoubleWordAccess: in isValidOffset()
330 case HexagonII::MemAccessSize::WordAccess: in isValidOffset()
333 case HexagonII::MemAccessSize::HalfWordAccess: in isValidOffset()
336 case HexagonII::MemAccessSize::ByteAccess: in isValidOffset()
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| D | HexagonPseudo.td | 522 multiclass NewCircularLoad<RegisterClass RC, MemAccessSize MS> {
543 multiclass NewCircularStore<RegisterClass RC, MemAccessSize MS> {
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| D | HexagonConstExtenders.cpp | 1084 uint8_t A = HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(F)); in getOffsetRange()
1124 uint8_t A = HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(F)); in getOffsetRange()
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| D | HexagonInstrInfo.cpp | 4151 unsigned Size = getMemAccessSizeInBytes(MemAccessSize(S)); in getMemAccessSize()
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| /external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonBaseInfo.h | 48 enum MemAccessSize { enum
275 static unsigned getMemAccessSizeInBytes(MemAccessSize S) { in getMemAccessSizeInBytes()
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| D | HexagonMCInstrInfo.cpp | 215 return HexagonII::getMemAccessSizeInBytes(HexagonII::MemAccessSize(S)); in getMemAccessSize()
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| /external/llvm/lib/Target/Hexagon/ |
| D | HexagonInstrFormats.td | 53 class MemAccessSize<bits<4> value> {
57 def NoMemAccess : MemAccessSize<0>;// Not a memory acces instruction.
58 def ByteAccess : MemAccessSize<1>;// Byte access instruction (memb).
59 def HalfWordAccess : MemAccessSize<2>;// Half word access instruction (memh).
60 def WordAccess : MemAccessSize<3>;// Word access instruction (memw).
61 def DoubleWordAccess : MemAccessSize<4>;// Double word access instruction (memd)
62 def Vector64Access : MemAccessSize<7>;// Vector access instruction (memv)
63 def Vector128Access : MemAccessSize<8>;// Vector access instruction (memv)
165 MemAccessSize accessSize = NoMemAccess;
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| D | HexagonInstrInfo.td | 1991 MemAccessSize AccessSz>
2098 class T_loadalign_pcr<string mnemonic, bits<4> MajOp, MemAccessSize AccessSz >
2240 MemAccessSize addrSize, bits<4> majOp>
3387 MemAccessSize AccessSz, bit isHalf = 0>
3662 MemAccessSize AlignSize, string RegSrc = "Rt">
3704 bits<2>MajOp, MemAccessSize AlignSize>
3740 MemAccessSize AlignSize, string RegSrc = "Rt">
3776 MemAccessSize AlignSize>
3807 MemAccessSize addrSize, bits<3> majOp,
3851 class T_storenew_pbr<string mnemonic, MemAccessSize addrSize, bits<2> majOp>
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| D | HexagonInstrInfoV4.td | 689 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
728 MemAccessSize AccessSz >
758 bits<3> MajOp, MemAccessSize AccessSz, bit isHalf = 0>
823 MemAccessSize AccessSz>
1381 class T_loadalign_pr <string mnemonic, bits<4> MajOp, MemAccessSize AccessSz>
1511 class T_StorePI_RegNV <string mnemonic, bits<2> MajOp, MemAccessSize AccessSz>
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| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| D | HexagonMCCodeEmitter.cpp | 389 case HexagonII::MemAccessSize::ByteAccess: in getFixupNoBits()
391 case HexagonII::MemAccessSize::HalfWordAccess: in getFixupNoBits()
393 case HexagonII::MemAccessSize::WordAccess: in getFixupNoBits()
395 case HexagonII::MemAccessSize::DoubleWordAccess: in getFixupNoBits()
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| D | HexagonMCInstrInfo.h | 29 enum class MemAccessSize; variable
93 HexagonII::MemAccessSize getAccessSize(MCInstrInfo const &MCII,
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| D | HexagonBaseInfo.h | 94 enum class MemAccessSize { enum
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| D | HexagonMCInstrInfo.cpp | 168 HexagonII::MemAccessSize
172 return (HexagonII::MemAccessSize((F >> HexagonII::MemAccessSizePos) & in getAccessSize()
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