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Searched refs:RegClass (Results 1 – 25 of 122) sorted by relevance

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/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/GlobalISel/
DUtils.cpp35 const TargetRegisterClass &RegClass) { in constrainRegToClass() argument
36 if (!RBI.constrainGenericRegister(Reg, RegClass, MRI)) { in constrainRegToClass()
37 unsigned NewReg = MRI.createVirtualRegister(&RegClass); in constrainRegToClass()
57 const TargetRegisterClass *RegClass = TII.getRegClass(II, OpIdx, &TRI, MF); in constrainOperandRegClass() local
66 if (RegClass && !RegClass->isAllocatable()) in constrainOperandRegClass()
67 RegClass = TRI.getConstrainedRegClassForOperand(RegMO, MRI); in constrainOperandRegClass()
69 if (!RegClass) { in constrainOperandRegClass()
85 return constrainRegToClass(MRI, TII, RBI, InsertPt, Reg, *RegClass); in constrainOperandRegClass()
/external/swiftshader/third_party/LLVM/lib/Target/
DTargetInstrInfo.cpp36 short RegClass = MCID.OpInfo[OpNum].RegClass; in getRegClass() local
38 return TRI->getPointerRegClass(RegClass); in getRegClass()
41 if (RegClass < 0) in getRegClass()
45 return TRI->getRegClass(RegClass); in getRegClass()
/external/swiftshader/third_party/LLVM/lib/Target/X86/
DX86InstrArithmetic.td515 /// RegClass - This is the register class associated with this type. For
517 RegisterClass RegClass = regclass;
606 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
613 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
614 [(set typeinfo.RegClass:$dst,
615 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
623 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
630 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
631 [(set typeinfo.RegClass:$dst, EFLAGS,
632 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/tools/llvm-exegesis/lib/
DRegisterAliasing.cpp34 const llvm::MCRegisterClass &RegClass) in RegisterAliasingTracker() argument
36 for (llvm::MCPhysReg PhysReg : RegClass) in RegisterAliasingTracker()
77 const auto &RegClass = RegInfo.getRegClass(RegClassIndex); in getRegisterClass() local
79 Found.reset(new RegisterAliasingTracker(RegInfo, ReservedReg, RegClass)); in getRegisterClass()
/external/swiftshader/third_party/LLVM/include/llvm/CodeGen/
DRegisterScavenging.h107 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
118 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
120 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister() argument
121 return scavengeRegister(RegClass, MBBI, SPAdj); in scavengeRegister()
/external/llvm/include/llvm/CodeGen/
DRegisterScavenging.h114 unsigned FindUnusedReg(const TargetRegisterClass *RegClass) const;
143 unsigned scavengeRegister(const TargetRegisterClass *RegClass,
145 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister() argument
146 return scavengeRegister(RegClass, MBBI, SPAdj); in scavengeRegister()
DRegisterClassInfo.h45 std::unique_ptr<RCInfo[]> RegClass; variable
71 const RCInfo &RCI = RegClass[RC->getID()]; in get()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/Hexagon/
DRDFRegisters.cpp37 if (RI.RegClass != nullptr && !BadRC[R]) { in PhysicalRegisterInfo()
38 if (RC->LaneMask != RI.RegClass->LaneMask) { in PhysicalRegisterInfo()
40 RI.RegClass = nullptr; in PhysicalRegisterInfo()
43 RI.RegClass = RC; in PhysicalRegisterInfo()
67 if (const TargetRegisterClass *RC = RegInfos[F].RegClass) in PhysicalRegisterInfo()
172 const TargetRegisterClass *RC = RegInfos[RR.Reg].RegClass; in aliasRM()
233 LaneBitmask RCM = RI.RegClass ? RI.RegClass->LaneMask in mapTo()
/external/llvm/lib/Target/X86/
DX86InstrArithmetic.td563 /// RegClass - This is the register class associated with this type. For
565 RegisterClass RegClass = regclass;
658 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
668 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
675 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
676 [(set typeinfo.RegClass:$dst, EFLAGS,
677 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))],
684 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst),
685 [(set typeinfo.RegClass:$dst, EFLAGS,
686 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/X86/
DX86InstrArithmetic.td537 /// RegClass - This is the register class associated with this type. For
539 RegisterClass RegClass = regclass;
629 (ins typeinfo.RegClass:$src1, typeinfo.RegClass:$src2),
639 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
645 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteALU,
646 [(set typeinfo.RegClass:$dst, EFLAGS,
647 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2))]>;
653 : BinOpRR<opcode, mnemonic, typeinfo, (outs typeinfo.RegClass:$dst), WriteADC,
654 [(set typeinfo.RegClass:$dst, EFLAGS,
655 (opnode typeinfo.RegClass:$src1, typeinfo.RegClass:$src2,
[all …]
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/AVR/InstPrinter/
DAVRInstPrinter.cpp107 bool isPtrReg = (MOI.RegClass == AVR::PTRREGSRegClassID) || in printOperand()
108 (MOI.RegClass == AVR::PTRDISPREGSRegClassID) || in printOperand()
109 (MOI.RegClass == AVR::ZREGRegClassID); in printOperand()
/external/swiftshader/third_party/subzero/pydir/
Dgen_arm32_reg_tables.py203 for _, RegClass in RegClasses:
204 for Reg in RegClass:
208 for _, RegClass in RegClasses:
209 for Reg in RegClass:
223 for Name, RegClass in RegClasses:
226 for Reg in RegClass:
/external/swiftshader/third_party/LLVM/lib/CodeGen/
DMachineRegisterInfo.cpp97 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister() argument
98 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
99 assert(RegClass->isAllocatable() && in createVirtualRegister()
109 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
DRegisterClassInfo.h41 OwningArrayPtr<RCInfo> RegClass; variable
65 const RCInfo &RCI = RegClass[RC->getID()]; in get()
DRegisterClassInfo.cpp37 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
71 RCInfo &RCI = RegClass[RC->getID()]; in compute()
/external/v8/src/wasm/baseline/
Dliftoff-register.h21 enum RegClass : uint8_t { enum
36 static inline constexpr RegClass reg_class_for(ValueType type) { in reg_class_for()
95 static LiftoffRegister from_code(RegClass rc, int code) { in from_code()
154 RegClass reg_class() const { in reg_class()
313 static constexpr LiftoffRegList GetCacheRegList(RegClass rc) { in GetCacheRegList()
/external/swiftshader/third_party/llvm-7.0/llvm/test/TableGen/
DRegisterEncoder.td15 def RegClass : RegisterClass<"foo", [i32], 0, (add Reg)>;
17 def RegOperand : RegisterOperand<RegClass> {
/external/swiftshader/third_party/subzero/src/
DIceTypes.h36 enum RegClass : uint8_t { enum
46 static_assert(RC_Target == static_cast<RegClass>(IceType_NUM),
86 const char *regClassString(RegClass C);
/external/llvm/lib/Target/AMDGPU/Disassembler/
DAMDGPUDisassembler.cpp51 #define DECODE_OPERAND2(RegClass, DecName) \ argument
52 static DecodeStatus Decode##RegClass##RegisterClass(MCInst &Inst, \
60 #define DECODE_OPERAND(RegClass) DECODE_OPERAND2(RegClass, RegClass) argument
/external/swiftshader/third_party/llvm-7.0/llvm/lib/Target/WebAssembly/
DWebAssemblyRegStackify.cpp103 const auto *RegClass = in ConvertImplicitDefToConstZero() local
105 if (RegClass == &WebAssembly::I32RegClass) { in ConvertImplicitDefToConstZero()
108 } else if (RegClass == &WebAssembly::I64RegClass) { in ConvertImplicitDefToConstZero()
111 } else if (RegClass == &WebAssembly::F32RegClass) { in ConvertImplicitDefToConstZero()
116 } else if (RegClass == &WebAssembly::F64RegClass) { in ConvertImplicitDefToConstZero()
582 const auto *RegClass = MRI.getRegClass(Reg); in MoveAndTeeForMultiUse() local
583 unsigned TeeReg = MRI.createVirtualRegister(RegClass); in MoveAndTeeForMultiUse()
584 unsigned DefReg = MRI.createVirtualRegister(RegClass); in MoveAndTeeForMultiUse()
587 TII->get(GetTeeOpcode(RegClass)), TeeReg) in MoveAndTeeForMultiUse()
/external/swiftshader/third_party/llvm-7.0/llvm/include/llvm/CodeGen/
DRegisterClassInfo.h48 std::unique_ptr<RCInfo[]> RegClass; variable
75 const RCInfo &RCI = RegClass[RC->getID()]; in get()
DRegisterScavenging.h163 unsigned scavengeRegister(const TargetRegisterClass *RegClass, int SPAdj) { in scavengeRegister() argument
164 return scavengeRegister(RegClass, MBBI, SPAdj); in scavengeRegister()
/external/llvm/lib/CodeGen/
DRegisterClassInfo.cpp42 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
81 RCInfo &RCI = RegClass[RC->getID()]; in compute()
DMachineRegisterInfo.cpp95 MachineRegisterInfo::createVirtualRegister(const TargetRegisterClass *RegClass){ in createVirtualRegister() argument
96 assert(RegClass && "Cannot create register without RegClass!"); in createVirtualRegister()
97 assert(RegClass->isAllocatable() && in createVirtualRegister()
103 VRegInfo[Reg].first = RegClass; in createVirtualRegister()
/external/swiftshader/third_party/llvm-7.0/llvm/lib/CodeGen/
DRegisterClassInfo.cpp51 RegClass.reset(new RCInfo[TRI->getNumRegClasses()]); in runOnMachineFunction()
93 RCInfo &RCI = RegClass[RC->getID()]; in compute()

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